Method for manufacturing a memory cell arrangement

Details Method for manufacturing a memory cell arrangement Method for manufacturing a memory cell arrangement

2008-06-18

2009-11-03

Pham, Hoai v (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S211000, C257SE21179, C257SE21422

Reexamination Certificate

active

07611941

ABSTRACT:
In an embodiment of the invention, a method for manufacturing a memory cell arrangement includes forming a charge storing memory cell layer stack over a substrate; forming first and second select structures over, respectively, first and second sidewalls of the charge storing memory cell layer stack, wherein the first and second select structures in each case comprise a select gate configured as a spacer and laterally disposed from the respective sidewall of the charge storing memory cell layer stack; and removing a portion of the charge storing memory cell layer stack between the first and second select structures after formation of the first and second select structures, thereby forming first and second charge storing memory cell structures.

REFERENCES:
patent: 6642103 (2003-11-01), Slotboom et al.
patent: 2002/0100926 (2002-08-01), Kim et al.
patent: 2004/0014284 (2004-01-01), Kim et al.
Chen, H-Y, et al., “Novel 20nm Hybrid SOI/Bulk CMOS Technology with 0.183μm26T-STRAM Cell by Immersion Lithography,” 2005 Symposium on VLSI Technology Digest of Technical Papers, 2005, pp. 16-17.
Mih, R., et al., “0.18um Modular Triple Self-Aligned Embedded Split-Gate Flash Memory,” 2000 Symposium on VLSI Technology Digest of Technical Papers, 2000, pp. 120-121.

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