Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-07-05
2011-07-05
Pham, Thanhha (Department: 2894)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S593000, C257SE21422
Reexamination Certificate
active
07972924
ABSTRACT:
A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.
REFERENCES:
patent: 2007/0004137 (2007-01-01), Oh
patent: 2009/0111229 (2009-04-01), Steimle et al.
patent: 200509376 (2005-03-01), None
patent: 200837896 (2008-09-01), None
Hsiao Ching-Nan
Huang Chung-Lin
Tsai Hung-Mine
Hsu Winston
Margo Scott
Nanya Technology Corp.
Pham Thanhha
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