Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-02-15
2004-03-02
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S228000, C438S286000, C438S301000, C438S585000
Reexamination Certificate
active
06699740
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method excellent at characteristics of break down voltage and on resistance and the like.
2. Description of the Related Art
An LDMOS (lateral double-diffused metal oxide semiconductor) transistor is well known as a power device that is small in size and low in power consumption. The publication of unexamined application, JP10-335663, discloses the structure and manufacturing method thereof.
A conventional LDMOS transistor is manufactured as follows. A P
−
-type epitaxial layer (a first region) is formed on a substrate of a P
+
-type semiconductor. A second region as an N
−
-type well is formed on the first region. A third region of P
−
-type as a D-well is formed inside the second region and a gate is formed on at least a part of the third region while an N-type RSD (reduced surface drain) region is formed inside the second region.
A first side of the RSD region matches a first side of the gate and spreads out of the gate. An N
+
-type source region and a P
+
-type back gate region are formed inside the third region. The third region is formed between a source region and the RSD region to form a channel. The source region is formed under a second side of the gate and spaced-from the RSD region. On the other hand, an N
+
-type drain region is formed inside the second region and spaced from the first side of the gate. The concentrations of the added impurity in the source region and drain region are higher than that in the RSD region.
In the steps of creating a photoresist patterning and depositing, introducing and diffusing of various kinds of materials, a semiconductor manufacturing technology that has been already known is used.
Generally in the LDMOS transistor, the resistance path is expressed by the sum of channel length L and drift length Ld, that is, L+Ld. When the drift length Ld changes, on resistance Rsp and breakdown voltage BV change accordingly, as disclosed in JP10-335663.
According to the conventional method for manufacturing an LDMOS transistor as described above, however, the gate and the drain region are respectively formed in different steps and by a photolithography technology, in which different masks are used. For this reason, the locations at which the gate region and the drain region are formed have to be aligned. Consequently, the displacement of alignment thereof occurs in the semiconductor manufacturing technology that has been already known. The displacement of alignment like this causes unequal values of the drift length Ld and an unstable characteristic of the semiconductor device in the process of mass-producing.
SUMMARY OF THE INVENTION
The object of the present invention to provide a novel and improved semiconductor device having a stable element characteristic without making the values of the drift length Ld unequal in manufacturing.
In the present invention to achieve the above object, there is provided a semiconductor device comprising: a semiconductor layer of a first conductive type; a first well of a second conductive type formed on the surface of the semiconductor layer; a second well of the first conductive type formed on the surface of the first well; a source region of the second conductive type formed on the surface of the second well; a drain region of the second conductive type formed on the surface of the first well and formed apart from the source region at a specific distance; a gate electrode formed on the semiconductor layer and extending from the source region to the second well and the first well; an application electrode arranged apart from the gate electrode, arranged on the first well between the second well and the drain region and extending from the first well to the edge of the first well contacting the drain region; and a first impurity diffusion layer of the first conductive type formed on the surface of the second well and reaching the second well under the source region.
It is to be noted that the first conductive type corresponds to P-type and the second conductive type to N-type, or conversely, the first conductive type may correspond to P-type and the second conductive type to N-type, as in the normal MOS transistor. These relations can be adopted to the following description.
Also in the present invention to achieve the above object, there is provided a method for manufacturing a semiconductor device comprising the steps of: forming a first well of a second conductive type on the surface of a semiconductor layer of a first conductive type surrounded by an element separated region; forming a second well of the first conductive type on the surface of the first well; forming a source region on the surface of the second well; forming a conductive film on the upper surface of the semiconductor layer; patterning the conductive film; forming a gate electrode on the semiconductor layer to extend from the source region to the second well and the first well; forming a mask on the first well arranged apart from the gate electrode; forming a first resist mask, the one end of which is arranged on the mask while the surface of the first well between the element separating region and the mask is exposed, on the semiconductor layer including the gate electrode and the mask; forming a drain region on the surface of the first well by introducing an impurity of the second conductive type with the first resist mask as a mask; forming a second resist mask, the one end of which is arranged on the mask while the surface of the first well between the element separating region and the mask is exposed, on the semiconductor layer including the gate electrode and the mask; and forming a second impurity diffusion layer, which has a concentration of an impurity lower than that of the drain region and which is connected to the drain region, on the surface of the first well by introducing an impurity of the second conductive type with the first resist mask as a mask.
REFERENCES:
patent: 2003/0040159 (2003-02-01), Sasaki
patent: 62-265765 (1987-11-01), None
patent: 1-199468 (1989-10-01), None
patent: 10-335663 (1998-12-01), None
patent: 11-31816 (1999-02-01), None
patent: 2000-216261 (2000-04-01), None
patent: 2001-307283 (2001-10-01), None
Patent Abstracts of Japan, Publication No. 2000-216261, Date of Publication of Application Apr. 8, 2000.
Patent Abstracts of Japan, Publication No. 11-031816, Date of Publication of Application Feb. 2, 1999.
Patent Abstracts of Japan, Publication No. 10-335663, Date of Publication of Application Dec. 18, 1998.
Patent Abstracts of Japan, Publication No. 01-199468, Date of Publication of Application Oct. 8, 1989.
Patent Abstracts of Japan, Publication No. 62-265765, Date of Publication of Application Nov. 18, 1987.
Chen Jack
Oki Electric Industry Co. Ltd.
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