Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-31
2004-08-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S306000
Reexamination Certificate
active
06773997
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to high voltage MOSFET semiconductor devices and more specifically to a method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability.
When designing high voltage metal oxide semiconductor (MOS) devices two criteria must be kept in mind. First, the semiconductor device should have a high breakdown voltage (V
BD
). Second, the semiconductor device, when operating, should have a low on-resistance (RDS
ON
). One problem is that techniques and structures that tend to maximize breakdown voltage tend to adversely affect on-resistance and vice versa.
Different designs have been proposed to create semiconductor devices with acceptable combinations of breakdown voltage and on-resistance. One such family of semiconductor devices is fabricated according to the reduced surface field (RESURF) principle. Semiconductor devices with RESURF typically utilize an extended drain region, such as an nwell, to support high off-state voltage, i.e. an increase in breakdown voltage, V
BD
. Such RESURF semiconductor devices can have a charge in the drain area of about 1×10
12
atoms/cm
2
before avalanche breakdown occurs. The charge sets up a low on-resistance since on-resistance is inversely proportional to the charge in the extended drain region.
To accomplish RESURF principle, some semiconductor devices utilize a top layer of a conductivity type opposite the extended drain region, such as a p-top layer, inside the extended drain region. The p-top layer allows the extended drain region to have approximately double the charge as compared to previous designs, which in turn decreases the on-resistance significantly. The p-top layer also depletes the extended drain region when the extended drain region is supporting high voltage, thus allowing for high breakdown voltage.
In the prior art, a thick layer of field oxide or other dielectric material, on the order of 1 micron in thickness, is formed along the drift region overlying the entire p-top layer region. Originally, the thick layer of field oxide was grown on the extended drain region to reshape the electric field distribution, commonly known as enhanced field plate effect, especially in the source and drain regions. The thick layer of field oxide also serves to protect the semiconductor device from damage by mobile ions or impurities.
However, it has been shown that the field oxide layer tends to consume the p-top layer. Since it is difficult to predict how much the p-top layer will be consumed by the growth of the field oxide layer, it makes the formation of the p-top layer in the extended drain region uncontrollable and unpredictable. If the p-top layer is consumed considerably, it would be difficult to deplete the extended drain region as effectively as required.
One solution is to increase the thickness of the p-top layer which will leave some p-top layer remaining even after partial consumption by the field oxide layer. However, the top portion of the extended drain region beneath the field oxide layer has a high concentration of dopants and therefore gives a low on-resistance. By increasing the thickness of the p-top layer, less of the high concentration underneath the p-top in the extended drain region is available, which will cause an increase in on-resistance.
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Enosawa Yoshio
Fulton Joe
Hossain Zia
Imam Mohamed
Stefanov Evgueniy
Niebling John F.
Roman Angel
Semiconductor Components Industries L.L.C.
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