Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-01
2001-05-22
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000
Reexamination Certificate
active
06235576
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87120601.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing a capacitor on a semiconductor substrate. More particularly, the present invention relates to a method for manufacturing a cylindrical capacitor that utilizes oxide spacers as a hard mask in a polysilicon etching operation.
2. Description of Related Art
As the processing power of microprocessors continues to grow at an exponential rate, the amount of data that can be processed by software programs at any one time increases correspondingly. Hence, the need for high capacity memories is imminent. At present, dynamic random access memories (DRAMs) are extensively used because they have a high storage capacity. Since each DRAM unit is composed of just a transfer field effect transistor (transfer FET) and a storage capacitor, DRAM can have a very high level of integration.
When the storage capacity of a DRAM is at the one megabit range or lower, a simple two-dimensional or planar type of capacitor design can be used in a memory unit. However, when fabricating higher capacity DRAMs, the simple two-dimensional capacitor design cannot reach the desired level of integration. This is because the combined surface area of all the capacitors would be much greater than the available substrate area on a silicon wafer. Consequently, for memory having a storage capacity greater than 4 megabits, three-dimensional capacitors are often used. One common type of three-dimensional capacitor is known as the stacked type, and a cylindrical capacitor belongs to the stacked type of capacitor.
FIGS. 1A through 1E
are schematic, cross-sectional views showing the progression of manufacturing steps according to the conventional method of producing the lower electrode of a cylindrical capacitor. First, as shown in
FIG. 1A
, a semiconductor substrate
10
having device structure such as a source/drain region
12
is provided. Thereafter, an insulation layer
14
is deposited over the semiconductor substrate
10
, and then a node contact opening
16
is formed in the insulation layer. Subsequently, polysilicon material is deposited into the node contact opening
16
and over the insulation layer
14
to form a polysilicon layer
18
. The node contact inside the node contact opening
16
connects electrically with the source/drain region
12
. After that, a photolithographic operation is carried out to form a photoresist layer
20
over the polysilicon layer
18
, and then the photoresist layer is patterned.
Next, as shown in
FIG. 1B
, a portion of the polysilicon layer
18
is etched away using the photoresist layer
20
as a mask. The amount of polysilicon to be removed can be controlled by adjusting the etching period. Ultimately, a protruding slab structure
22
is carved out of the polysilicon layer
18
. Subsequently, the photoresist layer
20
is removed.
Next, an insulation layer is formed over the polysilicon layer
18
and the protruding slab
22
as shown in FIG.
1
C. Thereafter, an anisotropic etching back operation is carried out to form spacers
24
on the sidewalls of the protruding slab
22
.
Next, as shown in
FIG. 1D
, a portion of the polysilicon layer
18
is etched away with the spacers
24
serving as a mask. The amount of polysilicon to be removed can also be controlled by adjusting the etching period. Consequently, a cylindrical-shaped structure
18
a
having a central hollow is formed. In general, horns
25
are also formed at the upper corner regions next to interior sidewalls of the spacers
24
.
Finally, as shown in
FIG. 1E
, a wet etching operation is carried out to remove the spacers
24
so that the cylindrical-shaped structure
18
a
remains. The cylindrical-shaped structure
18
a
serves as the lower electrode of a capacitor. Thereafter, a dielectric layer
26
is formed over the lower electrode
18
a
, and then a polysilicon layer
28
is formed over the dielectric layer
26
to complete the fabrication of a capacitor structure
29
. The polysilicon layer
28
serves as the upper electrode of the capacitor.
In the aforementioned method of forming a lower electrode structure, horn structures
25
are easily formed on the upper edges of the cylindrical-shaped structure
18
a
. Sometimes the sharp horns
25
may break, and hence may become a source of contaminants when the substrate is immersed in an acid bath for forming the dielectric layer
26
. On the other hand, even if the horn structures
25
are not broken off, the accumulation of charges there may lead to serious current leakage problems.
In light of the foregoing, there is a need to provide an improved method for manufacturing a cylindrical capacitor structure.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a method for manufacturing a cylindrical capacitor on a substrate that utilizes oxide spacers as a mask when etching a polysilicon layer. The method is capable of eliminating unwanted horns that conventionally form on the upper comer regions of the lower electrode of a capacitor, thereby reducing current leakage problems. Moreover, the cylindrical capacitor has a higher effective coupling area so that a higher capacitance is obtained.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for manufacturing a cylindrical capacitor on a substrate. The method includes the steps of providing a semiconductor substrate that has a source/drain region thereon, and then forming a first insulation layer over the substrate. Thereafter, a node contact opening is formed in the first insulation layer, and then a first conductive layer that fills the node contact opening and covers the first insulation layer is formed. The first conductive layer inside the node contact opening forms a node contact that connects electrically with the source/drain region. A second insulation layer is formed over the first conductive layer, and then the second insulation layer is patterned such that the remaining second insulation layer covers the region above the node contact. Spacers are formed on the sidewalls of the patterned second insulation layer. The spacers are made from material that differs from the second insulation layer and the first conductive layer. Thereafter, an anisotropic etching operation is conducted using the patterned second insulation layer and the spacers as a mask to remove a portion of the first conductive layer. A protruding structure is carved out of the first conductive layer. The protruding structure is formed above the node contact opening as well. After that, the patterned second insulation layer is removed. Then, a second anisotropic etching operation is carried out using the spacers as a mask and the first insulation layer as an etch stop layer to remove a portion of the first conductive layer. A cylindrical structure that serves as the lower electrode of a capacitor is formed. The spacers are removed, and then a dielectric layer and a second conductive layer are sequentially formed over the cylindrical lower electrode to complete the fabrication of the cylindrical capacitor.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5447881 (1995-09-01), Ryou
Chen Anchor
Hong Gary
Gurley Lynne A.
Huang Jiawei
J.C. Patents
Niebling John F.
United Microelectronics Corp.
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