Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-11-25
1998-11-24
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438398, H01L 218242
Patent
active
058406069
ABSTRACT:
A method for manufacturing a comb-shaped lower electrode for a DRAM capacitor including the steps of providing a substrate having a transistor and an insulating layer formed thereon, wherein the insulating layer contains a contact window opening exposing a source/drain region of the transistor; then, forming a polysilicon layer over the insulating layer, the contact window opening and the exposed source/drain region; next, forming a hemispherical grain silicon over the polysilicon layer. Thereafter, an oxide layer is formed over the hemispherical grain silicon, and then a silicon nitride layer is formed over the gaps between the hemispherical grain silicon exposing portions of the oxide layer. In the subsequent step, a plurality of hard mask layers are formed over the oxide layer not covered by the silicon nitride layer, and finally the silicon nitride layer, the oxide layer and portions of the polysilicon layer are removed using the hard mask layers to form a plurality of trenches.
REFERENCES:
patent: 5670405 (1997-09-01), Tseng
patent: 5670407 (1997-09-01), Tseng
Chang Joni Y.
Niebling John
United Semiconductor Corp.
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