Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-28
2003-12-23
Fahmy, Wael (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S387000, C438S396000
Reexamination Certificate
active
06667208
ABSTRACT:
BACKGROUND
1. Technical Field
A method for manufacturing a semiconductor device is disclosed, and more particularly, a method for manufacturing a semiconductor device is disclosed in which the forming of the lower electrode of a capacitor is improved which, in turn, improves the subsequent process steps required to complete the formation of the capacitor.
2. Description of the Related Art
A memory device such as a dynamic random access memory DRAM, has greater integration than other kinds of memory devices. As the integration of these and other semiconductor devices increases, the design rule becomes more minute and a higher processing technique is required.
The cell of the DRAM basically comprises a transistor and a capacitor. The capacitor is the means for storing information, and a large capacitance per unit area is required.
Moreover, since reliability when storing information has to be guaranteed, undesirable phenomena such as current leakage caused by residual polysilicon should be reduced as much as possible as explained below in reference to
FIGS. 1 and 2
.
FIG. 1
is a cross sectional view of a semiconductor device, which illustrates the conventional method for manufacturing a semiconductor device.
As shown in
FIG. 1
, a nitride layer
16
and an oxide layer
17
for forming a capacitor are deposited on the bit lines of a semiconductor device formed with transistors and the bit lines on a cell area A and a peripheral circuit area B. Then, an area on which to form a capacitor is defined on the cell area A, and a polysilicon layer
18
for forming a lower electrode of the capacitor is deposited on the entire construction.
Then, the polysilicon layer
18
for forming the lower electrode of the capacitor on the peripheral circuit area B is etched, wherein the etching gas is a mixture of CF
4
gas of about 300 sccm and O
2
gas of about 100 sccm, the temperature is about 10° C., the pressure is about 400 mTorr, and the electrical power of high frequency for generating plasma is about 700 W.
In such a situation, a natural oxidation layer
19
formed by the etching gas may remain on the lower portion of the peripheral circuit area B, and the remaining natural oxidation layer
19
functions as an anti-etching layer causing residual polysilicon layer
18
on the undesirable portion as shown in FIG.
1
.
As a result, the remaining polysilicon layer
18
causes defects during subsequent process steps where the oxidation layer for forming the capacitor is removed by wet etching.
If the etching is performed excessively in removing the natural oxidation layer
19
on the peripheral circuit area B, the etching time increases. Moreover, in such a situation, the polysilicon layer
18
for forming the lower electrode may be etched together with the photosensitive layer on the cell area A, which results in the decrease in the height of the lower electrode and a reduction of the capacitance of the capacitor.
SUMMARY OF THE DISCLOSURE
A method for manufacturing a semiconductor device is disclosed, in which a photosensitive layer and a natural oxidation layer on a cell area and a peripheral circuit area are removed by dry etching while a capacitor of a DRAM device is manufactured, and a polysilicon layer which is not used in the following process is removed by controlling the composition ratio of CF
4
gas and O
2
gas and the change in pressure and electrical power in two steps so as to reduce the etching selection ratio of the photosensitive layer and the natural oxidation layer with respect to the polysilicon, whereby residual polysilicon is prevented regardless of the etching time and etching amount.
A method for forming a semiconductor device is disclosed which comprises: preparing a semiconductor device formed with a transistor and a bit line on the cell area and peripheral circuit area; depositing a nitride layer and an oxide layer for forming a capacitor on the bit line; defining a part to form a capacitor on the cell area, and depositing a polysilicon layer for forming a lower electrode of the capacitor on an entire construction; depositing a photosensitive layer on the cell area, and performing a multiple isotropic etching on the polysilicon layer for forming the lower electrode of the capacitor on the peripheral circuit area with a mixture of CF
4
gas and O
2
gas; depositing a gap-fill oxide layer on the entire construction, and performing a chemical and mechanical polishing to leave the gap-fill oxide layer only on a gap portion of the polysilicon layer for forming the lower electrode of the capacitor on the cell area; and forming the lower electrode of the capacitor by etching an overall exposed part of the polysilicon layer.
In performing the two steps of etching of the polysilicon layer for forming the lower electrode of the capacitor on the peripheral circuit area with the mixture of CF
4
gas and O
2
gas, the first etching step is performed with the mixture of CF
4
gas and O
2
gas of a ratio is in the range of 0.8-1.2:0.8-1.2, for about 30 seconds at a temperature ranging from about 30° C. to about 40° C. and at a pressure ranging from about 800 mTorr to about 900 mTorr, by supplying an electrical power of high frequency ranging from about 800 W to about 900 W, and the second etching step is performed with the mixture of CF
4
gas and O
2
gas of a ratio in the range 4.5-5.5:1.2-2.5, for about 45 seconds at a temperature ranging from about 30° C. to about 40° C. and at a pressure ranging from about 350 mTorr to about 450 mTorr, by supplying an electrical power of high frequency ranging from about 600 W to about 700 W. Then, the etching selection ratio in regard to the polysilicon for forming the lower electrode of the capacitor on the peripheral circuit area B, the natural oxidation layer (not shown), and the photosensitive layer
130
becomes 7-7.6:0.8-1.2:2.8-3.3.
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patent: 2001/0035552 (2001-11-01), Onishi
Kim Jung-guk
Nam Ki-won
Oh Sang-ryong
Park Jin-ho
Fahmy Wael
Hynix Semiconductor Inc
Marshall & Gerstein & Borun LLP
Smoot Stephen W.
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