Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-28
2003-05-27
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S240000, C438S247000, C438S251000, C438S252000, C438S381000, C257S296000, C257S297000, C257S298000, C257S299000, C257S300000, C257S301000, C257S303000
Reexamination Certificate
active
06569728
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for forming a semiconductor capacitor and, more particularly, to a capacitor in a metal insulator silicon (MIS) structure.
DESCRIPTION OF THE PRIOR ART
Recently, a Ta
2
O
2
layer has been used as a dielectric layer of a capacitor. A Ta
2
O
2
material of a high dielectric constant has been substituted for a nitride oxide (NO) material in forming a semiconductor capacitor.
FIG. 1
is a cross-sectional view illustrating a conventional capacitor in a metal insulator silicon (hereinafter, referred to as a MIS) structure. A polysilicon layer is used as a bottom electrode of a semiconductor capacitor for a storage electrode
11
, a metal layer is used as a top electrode for a plate electrode
13
and a Ta
2
O
2
layer is used as a dielectric layer
12
between the storage electrode
11
and the plate electrode
13
. As stated above, in the MIS structure, the polysilicon and metal layers are respectively used as the storage electrode
11
and the plate electrode
13
to overcome some difficulties in the metal electrode etching process and junction in a polysilicon substrate
10
.
However, in the MIS structure, due to a difference in work function and resistance between the storage electrode and the plate electrode, electric characteristics of the capacitor have a lot of polarity according to a bias. That is, if a plus bias is applied to the storage electrode, a depletion layer to decrease the capacitance thereof is formed in the surface between the Ta
2
O
5
layer and the storage electrode because the polysilicon layer is used as the storage electrode. Since the metal electrode has a larger work function than that of the polysilicon electrode, when a bias is applied to the plate electrode, electric characteristics of leakage current and an insulation destroying voltage deteriorate.
The decrease of capacitance, which is caused by the depletion layer, may be prevented by a high doping concentration in the polysilicon layer for the storage electrode. However, it is difficult to increase concentration of P more than 5×10
20
/cm
3
based on the conventional doped polysilicon deposition. Further, an excessive injection of PH
3
into a reaction chamber to obtain a concentration of 1×10
21
/cm
3
decreases the deposition rate, so a sufficient thickness of 200 Å or more may not be obtained and particles from anti-reacting sources causing an allied nuclei reaction may be generated.
Also, if a Ta
2
O
2
layer is deposited on the storage electrode, a low dielectric constant layer, SiO
2
, is formed on the polysilicon so that the capacitance of the capacitor is decreased.
To compensate for the above problems, a meta stable polysilicon (MPS) layer is employed on the storage electrode, but a low P concentration of the storage electrode is needed for the use of such a layer and, since the result is capacitance, then a capacitance difference to the bias, &Dgr;C, becomes greater. As described above, to use the MPS layer to increase the size of the capacitor, the P concentration of the storage electrode may be kept lower than 1×10
20
/cm
3
and the capacitance decrease caused by the depletion layer has an amount of 15%~30%, compared to that with no depletion layer.
On the other hand, although a metal insulator metal (MIM) structure is also used, which uses the same metal layers in the storage electrode and the plate electrode, there are many difficulties in forming a storage electrode pattern.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for forming a semiconductor capacitor which prevents the generation of a low dielectric constant layer and a capacitance decrease by a depletion layer and provides a capacitor with a high quality degree of integration.
In accordance with an aspect of the present invention, there is provided a method for forming a capacitor, the method comprising steps of a) stacking impurity-doped polysilicon layers which have a different concentration, thereby forming a bottom electrode; b) treating surfaces of the bottom electrode for preventing a low dielectric constant material from being generated on the surface of the bottom electrode; and c) forming a dielectric layer and a top electrode on the bottom electrode.
REFERENCES:
patent: 5338951 (1994-08-01), Argos, Jr. et al.
patent: 6027967 (2000-02-01), Parekh et al.
patent: 6201276 (2001-03-01), Agarwal et al.
patent: 6204203 (2001-03-01), Narwankar et al.
patent: 6303434 (2001-10-01), Parekh et al.
patent: 6303455 (2001-10-01), Hou et al.
S. J. Wang et al., Effects of Poly Depletion On the Estimate of Thin Dielectric Lifetime., Electron Device Letters. vol. 12 No. 11.*
K. F, Schyegraf et al. Impact of Polysilicon Depletion in Thin Oxide MOS Technology. 1993 VLITSA. pp 86-89.
Jin Seung-Woo
Lee Tae-Hyeok
Oh Hoon-Jung
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
Keshavan Belur
Smith Matthew
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