Method for making self-aligned node contacts to bit lines for ca

Details Method for making self-aligned node contacts to bit lines for ca Method for making self-aligned node contacts to bit lines for ca

1998-04-24

1998-11-17

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438396, H01L 218242

Patent

active

058375775

ABSTRACT:
A method for making memory cells having self-aligned node contacts to bit lines was achieved. After forming the array of FETs for the memory cells, a first insulating layer is deposited and planarized. A single masking step is used to concurrently etch bit lines and node contact openings for crown capacitors. A second polysilicon layer and a silicide layer are deposited to form a polycide layer which is specially patterned to form bit lines with portions of the polycide layer extending over the node contacts. A second insulating layer (e.g., BPSG) is deposited and openings are etched aligned over the node contacts to the polycide. The polycide is selectively etched in the openings to electrically isolate the individual bit lines and concurrently form self-aligned node contacts. A third insulating layer is deposited and etched back to form insulating sidewall liners on the bit lines. A third polysilicon layer is deposited and polished back to form an array of bottom electrodes in the openings for crown capacitors. An interdielectric layer and a fourth polysilicon layer are deposited, and the fourth polysilicon layer is patterned to complete the array of crown capacitors for the DRAM device.

REFERENCES:
patent: 5346844 (1994-09-01), Cho et al.
patent: 5668038 (1997-09-01), Huang et al.

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