Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-12-10
1998-07-21
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438226, 438227, 438229, 438299, 438491, 438659, 438660, 438663, 438670, H01L 218238
Patent
active
057834695
ABSTRACT:
A method of fabricating an integrated circuit in which nitrogen is incorporated into the gate dielectric and transistor gate. The method comprises the providing of a semiconductor substrate that has a p-well and a laterally displaced n-well, each including a channel region laterally displaced between a pair of source/drain regions. Preferably, the semiconductor substrate has a resistivity of approximately 10 to 15 .OMEGA.-cm. A dielectric layer is formed on an upper surface of the semiconductor substrate. The formation of the dielectric layer preferably comprises a thermal oxidation performed at a temperature of approximately 600.degree. to 900.degree. C. and the resulting thermal oxide has a thickness less than approximately 50 angstroms. A conductive gate layer is then formed on the dielectric layer. In a preferred embodiment, the conductive gate layer is formed by chemically vapor depositing polysilicon at a pressure of less than approximately 2 torrs at a temperature in the range of approximately 500.degree. to 650.degree. C. A nitrogen bearing impurity distribution is then introduced into the conductive gate layer and the dielectric layer. The introduction of the nitrogen bearing impurity distribution is suitably accomplished by implanting a nitrogen bearing molecule such as N, N.sub.2, NO, NF.sub.3, N.sub.2 O, NH.sub.3, or other nitrogen bearing molecule. Ideally, a peak concentration of the nitrogen bearing impurity distribution is in the range of approximately 1.times.10.sup.15 to 1.times.10.sup.19 atoms/cm.sup.3 and is located proximal to an interface of the conductive gate layer and the dielectric layer. Thereafter, an anneal may be performed, preferably in a rapid thermal process, at a temperature of approximately 900.degree. to 1100.degree. C. for a duration of less than 5 minutes.
REFERENCES:
patent: 4525920 (1985-07-01), Jacobs et al.
patent: 4613885 (1986-09-01), Haken
patent: 4774197 (1988-09-01), Haddad et al.
patent: 5189504 (1993-02-01), Nakayama et al.
patent: 5468666 (1995-11-01), Chapman
patent: 5508532 (1996-04-01), Teramoto
patent: 5554871 (1996-09-01), Yamashita et al.
Gardner Mark I.
Gilmer Mark C.
Advanced Micro Devices , Inc.
Daffer Kevin L.
Niebling John
Pham Long
LandOfFree
Method for making nitrogenated gate structure for improved trans does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for making nitrogenated gate structure for improved trans, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making nitrogenated gate structure for improved trans will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1646467