Method for making memory cell without halo implant

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S705000

Reexamination Certificate

active

07001811

ABSTRACT:
Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

REFERENCES:
patent: 6255219 (2001-07-01), Xiang et al.
Ohsawa, Takashi et al., Memory Design Using a One-Transistor Gain Cell on SOI, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, ISSN: 0018-9200, pp. 1510-1522.
Thompson, Scott, et al., “MOS Scaling: Transistor Challenges for the 21stCentury”, Intel Technology Journal Q3'98. 19pgs.
Ohsawa, Takashi et al., “ISSCC 2002/Session 9/Dram and Ferroelectric Memories / 9.1”, Memory LSI Research and Development Center, Yokohama, Japan. 3pgs.
Brand, A., “Intel's 0.25 Micron, 2.0Volts Logic Process Technology”, Intel Technology Journal Q3'98. 9pgs.

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