Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-06-23
2001-03-06
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S305000, C438S307000
Reexamination Certificate
active
06197643
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a level converting circuit for converting a level of an input signal, an internal potential generating circuit for generating an internal potential, an internal potential generating unit for generating an internal potential, a semiconductor device and method of manufacturing a transistor. More specifically, it relates to a level converting circuit capable of preventing through current, an internal potential generating circuit providing higher efficiency in generating internal potential, an internal potential generating unit facilitating setting of performance, a highly reliable semiconductor device and to a method of manufacturing a transistor having high breakdown voltage.
2. Description of the Background Art
Conventional level converting circuits are disclosed, for example, in Japanese Patent Laying-Open Nos. 4-223713, 4-269011 and 2-37823.
FIG. 75
is a schematic diagram showing a conventional level converting circuit.
Referring to
FIG. 75
, the conventional level converting circuit includes PMOS transistors
3
and
9
, NMOS transistors
5
and
13
, and an inverter
17
. PMOS transistor
3
and NMOS transistor
5
are connected in series between a ground node and a node having boosted potential Vpp.
PMOS transistor
9
and NMOS transistor
13
are connected in series between the ground node and the node having boosted potential Vpp. PMOS transistor
3
has its gate connected to the drain of NMOS transistor
13
. PMOS transistor
9
has its gate connected to the drain of NMOS transistor
5
.
A signal IN is input to the gate of NMOS transistor
5
. A signal IN inverted by inverter
17
is input to the gate of NMOS transistor
13
. A node between PMOS transistor
9
and NMOS transistor
13
is an output node, and a level converted signal OUT is output therefrom.
The operation will be described. The signal IN is a clock signal setting power supply potential Vcc and ground potential GND to “H” (high) level and “L” (low) level, respectively. When the signal IN is at the “H” level, NMOS transistor
5
and PMOS transistor
9
turn on. Thus, the signal OUT having the level of the boosted potential Vpp is output. More specifically, the signal IN having the level of power supply potential Vcc is converted to be the signal OUT having the higher level, that is, the level of the boosted potential Vpp.
When the signal IN is at the “L” level, PMOS transistor
3
and NMOS transistor
13
turn on. Therefore, the signal OUT having the level of the ground potential is output.
However, in the conventional level converting circuits, sometimes PMOS transistor
3
and NMOS transistor
5
or PMOS transistor
9
and NMOS transistor
13
may simultaneously be turned on. When the signal IN is at “L” level, NMOS transistor
5
and PMOS transistor
9
are off. If the signal IN attains to the “H” level next, it is possible that PMOS transistor
9
and NMOS transistor
5
turn on before PMOS transistor
3
and NMOS transistor
13
turn off.
When the signal IN is at the “H” level, PMOS transistor
3
and NMOS transistor
13
are off. It is possible that PMOS transistor
3
and NMOS transistor
13
turn on before PMOS transistor
9
and NMOS transistor
5
turn off, when the next “L” level signal IN is input.
From the foregoing, the conventional level converting circuit experiences the problem that through current flows from the node having boosted potential Vpp to the ground node.
SUMMARY OF THE INVENTION
The present invention was made to solve such a problem, and its object is to provide a level converting circuit which can prevent through current.
Another object of the present invention is to provide an internal potential generating circuit capable of generating internal potential efficiently.
A further object of the present invention is to provide an internal potential generating unit which allows switching of performance easily.
A still another object of the present invention is to provide a highly reliable semiconductor device.
A still further object of the present invention is to provide a method of manufacturing a highly reliable transistor which is not broken even when a high voltage is applied.
The internal potential generating circuit in accordance with the first aspect of the present invention includes a level converting circuit for outputting, in accordance with a signal of a first level input as a pulse, a signal of a second level as a pulse, the level converting circuit being connected between a first node having the second level potential serving as a supply source of the second level signal output therefrom, and a second node having a third level potential. The level converting circuit includes a level shift circuit outputting the second level signal in accordance with the first level signal, including an input portion to which the first level signal is input and an output portion for outputting the second level signal in accordance with the input of the first level signal to the input portion. The input portion or the output portion is set to a state in which current flows through in accordance with transition of the first level signal. The level shift circuit further includes a first current cutting circuit connected between the level shift circuit and a first node, and a second current cutting circuit connected between the level shift circuit and a second node. The first current cutting means cuts current path between the first node and the input portion before the first level signal is input, and cuts current path between the first node and the output portion before input of the first level signal is stopped. The second current cutting means cuts current path between the second node and the output portion before the first level signal is input, and cuts the current path between the second node and the input portion before input of the first level signal is stopped. The internal potential generating circuit further includes a pumping circuit for intermittently outputting charges in accordance with the second level signal output as the pulse from the level converting circuit. The third node, which is the output node of the pumping circuit is set at the second level potential as an internal potential by the intermittently output charges, the first node and the third node being connected to each other. The pumping circuit includes a charge transmitting transistor having its control electrode connected to a fourth node of which potential changes in response to the signal of the second level output as the pulse from the level converting circuit. The charge transmitting transistor turns on when the potential at the fourth node attains to a fourth level in accordance with the output of the second level signal and outputs charges to the third node, with an absolute value of potential difference between the fourth level potential and the second level potential being greater than the absolute value of the threshold voltage of the charge transmitting transistor.
As described above, in the internal potential generating circuit in accordance with the first aspect of the present invention, the level converting circuit cuts current path between a first node having a second level potential and a second node having a third level potential, before a through current flows therethrough. Therefore, through current between the first and second nodes can be prevented.
Further, the charge transfer transistor of the pumping circuit turns on when it receives, at its control electrode, a fourth level potential and output charges to the third node. Therefore, the third node attains to the second level potential.
The absolute value of the difference between the fourth level potential and the second level potential is greater than the absolute value of the threshold voltage of the charge transfer transistor. The third node and the first node are connected, and the level converting circuit outputs the second level signal based on the second level potential at the third node.
Since the absolute value of the difference between the
Asakura Mikio
Hidaka Hideto
Komiya Yuichiro
Ooishi Tsukasa
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Pham Long
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