Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-08
2001-08-07
Lebentritt, Michael (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S205000, C438S239000, C438S361000, C438S366000, C438S564000
Reexamination Certificate
active
06271068
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to integrated circuit semiconductor devices, and more particularly to a method for making bipolar transistors having improved emitters in bipolar/CMOS devices. This novel method results in bipolar transistors having emitters with shallower junction depths and better process control of the junction depth. These shallower junction depths are useful for submicrometer high-speed BiCMOS circuits in which the bipolar transistor performance is improved, for example, by increasing the breakdown (punchthrough) voltage, increasing the cutoff frequency, while maintaining a reasonable current gain.
(2) Description of the Prior Art
BiCMOS circuits are formed by integrating bipolar transistors and complementary metal on silicon (CMOS) field effect transistor (FET) devices on the same silicon chip. The CMOS devices provide low power and high density for digital applications, while bipolar transistors (current switch) require high power consumption and provide higher off-chip drive currents and lower logic swings. Many of the application-specific integrated circuits (ASIC) take advantage of these opposing properties by integrating the bipolar transistors and FET devices on the same silicon chip.
However, one problem on integrating the two devices on the same chip is optimizing the electrical characteristics of one device without adversely affecting the electrical characteristics of the other device. In one approach, to save process steps it is desirable to form the FET gate electrodes and concurrently to form the doped polysilicon emitter for the bipolar transistor. It is necessary to use a rapid thermal anneal (RTA) to activate the dopant implant for the FET source/drain contacts for low contact resistance after forming the FET gate electrodes and the bipolar emitter. However, this RTA makes it difficult to control the shallow diffused emitter junction depth to achieve a high-performance bipolar transistor.
Several methods for making bipolar transistors in BICMOS circuits are described in the literature. For example, in U.S. Pat. No. 5,773,340 to Kumauchi et al., a phosphorus-doped amorphous silicon layer is deposited and annealed to convert the amorphous silicon into a polysilicon for doping the bipolar emitter. The phosphorus present in the amorphous silicon is diffused into the bipolar active base region, followed by a high-temperature/short-time annealing to activate the impurity dopants for the source/drain regions of the MOS-FETs. In the invention U.S. Pat. No. 5,874,333 to Chang et al. a method is described for forming a doped polysilicon layer having a less rough upper layer. This is achieved by depositing the polysilicon layer at a high temperature (about 630° C.) and, without interrupting the deposition process, the temperature is ramped down to 560° C. to provide a smooth surface having minimal grain growth. In U.S. Pat. No. 5,953,600 to Gris the FETs are formed prior to forming the bipolar transistor. This allows the source/drain contacts to be activated by RTA prior to forming the shallow emitters for the bipolar transistor. However, this process requires additional process steps. In U.S. Pat. No. 5,028,557 to Tsai et al. a reverse self-aligned BICMOS circuit is described in which polysilicon source/drain contacts for the FETs are formed by out-diffusion and the extrinsic base for the bipolar transistor are made prior to forming the polysilicon emitter self-aligned to the extrinsic base (polysilicon) contacts. In U.S. Pat. No. 5,466,615 to Tsai a protective block layer is formed over the substrate where the FET gate electrode and bipolar transistor emitter areas are to be formed. This patent also uses a reversed self-aligned process to form the BiCMOS circuit. In U.S. Pat. No. 6,004,855 to Pollock et al. a high-performance bipolar transistor structure is described in which an interdigitated collector is made self-aligned to the emitter over the active base area. The invention does not address the integration of this bipolar transistor with CMOS devices.
However, there is still a need in the industry to provide a process for making BiCMOS circuits having bipolar transistors with shallower diffused junctions while being able to accurately control the emitter junction depth (fine tune) without adversely affecting electrical characteristics of the other devices on the chip. It is also important to achieve this goal while maintaining a cost-effective manufacturing process for making the BiCMOS circuits.
SUMMARY OF THE INVENTION
A principal object of the present invention is to make improved bipolar transistors with shallow emitter junctions for submicron high-speed BiCMOS circuits.
A second objective of this invention is to utilize a stacked amorphous silicon/polysilicon layer in the emitter structure, which allows shallower emitter junction depths to be achieved while using a rapid thermal anneal process. This allows the shallow emitter junction depths to be fine tuned for the specific circuit application while achieving low contact resistance source/drain contacts for the FETs.
A third objective of this invention is to provide a process that is easy to integrate into the current BiCMOS process without significantly increasing process complexity.
This novel invention is a method for making a BiCMOS circuit, and more specifically for making a stacked amorphous silicon/polysilicon emitter with more controllable shallow diffused junction depths for the bipolar transistor. Further, by adjusting the rapid thermal anneal (RTA) parameters at a later process step, the emitter junction depth can be varied to optimize bipolar electrical characteristics while activating the implanted dopant in the source/drain areas for the BiCMOS circuit.
The process sequence for making the BiCMOS starts by providing a P
−
single-crystal silicon substrate in which N
+
and P
+
buried layers are formed. An N
−
epitaxial layer is grown on the substrate. Next P wells and N wells are implanted respectively in the N
−
epitaxial layer over some portions the N
+
buried layers and the P
+
buried layers in which the N channel and P channel FETs for the CMOS portion of the BiCMOS circuit are formed. Next, a field oxide is formed to surround and electrically isolate the N channel and P channel device areas, and to provide isolation around the bipolar transistor device areas over portions of the N
+
buried layer. The bipolar transistors are fabricated in the N
−
epitaxial layer over these portions of the N
+
buried layers. First, a reachthrough or sinker implant is carried out to form contacts to the N
+
buried layers which serves as the subcollector of the bipolar transistors. A polysilicon layer, having a cap insulating layer, is deposited and patterned to form polysilicon resistors and capacitors, and a gate oxide and the first part of a split polysilicon deposition is carried out to protect the gate oxide. The base regions are implanted in the N
−
epitaxial layer over the subcollectors and in proximity to the sinker implant. Emitter openings are etched to the base regions. Next, and a key feature of this invention is to form a stacked undoped amorphous silicon/polysilicon layer in a single deposition step. The polysilicon upper portion of the stacked layer is then implanted without implanting the underlying undoped amorphous silicon layer. The stacked layer is patterned to form polysilicon emitters for the bipolar transistor while concurrently forming FET gate electrodes. Then the lightly doped drains (LDDs), sidewall spacers, and source/drain contacts for the FETs are formed. An interlevel dielectric (ILD) layer is deposited and leveled by annealing, while the undoped amorphous silicon layer prevents the diffusion of the emitter from the doped polysilicon emitter into the intrinsic base region on and in the substrate. Next, contact openings are etched in the ILD layer to the contact areas on the substrate. Another key feature of this invention is to carry out a ra
Hsu Yung-Lung
Liou Ruey-Hsin
Ackerman Stephen B.
Lebentritt Michael
Saile George O.
Taiwan Semiconductor Manufacturing Company
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