Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-19
2003-01-28
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S221000, C438S225000
Reexamination Certificate
active
06511887
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to semiconductor integrated circuit devices, and more particularly to a method for making field effect transistors (FETs) with different gate oxide thicknesses for various integrated circuit applications, such as forming a thicker tunnel oxide for non-volatile (flash) memory while providing a thinner gate oxide for high-performance logic circuits. The method uses a patterned thin silicon nitride (Si
3
N
4
) layer and a single oxidation step to provide a good quality thicker FET tunnel gate oxide while concurrently forming a good quality thinner FET gate oxide for the high-speed CMOS logic.
(2) Description of the Prior Art
Merged semiconductor logic and memory circuits are finding extensive use in the electronics industry for merged logic/memory devices. These deep submicrometer circuits require different gate oxide thicknesses to optimize the FET performance. Typically flash (non-volatile) memory and peripheral input-output (I/O) circuits require a thicker gate oxide, while CMOS logic circuits require a thinner gate oxide for increased performance (switching speed). For example, flash memory and peripheral circuits require a thicker oxide of 50 Angstroms or more and operate at a gate voltage of about 3.0 to 5.0 volts, while CMOS logic devices have effective gate oxides that are less than 25 Angstroms and operate at lower gate voltages (V) of between about 1.8 V and 2.5 V to achieve higher switching speeds.
One prior art method of achieving dual-thickness gate oxides for FETs is depicted in the schematic cross-sectional views of
FIGS. 1 and 2
. A field oxide
12
is formed in and on the silicon substrate
10
using conventional means to surround and electrically isolate the logic device areas L, as shown in the right potion of
FIG. 1
, and as shown in the left portion of
FIG. 1
for the memory and peripheral device areas M. A first gate oxide
13
is grown on both the logic and memory/peripheral device areas. Next, as shown in
FIG. 2
, a photoresist mask
16
is used to mask the gate oxide
13
over the memory device areas M, and then a wet etch is used to remove the gate oxide
13
over the logic device areas L. The photoresist mask
16
is then removed by plasma ashing and/or by stripping in a photoresist stripper. Unfortunately, the photoresist
16
in direct contact with the thin gate oxide
13
on the silicon substrate
10
surface results in contamination that causes reliability problems. Next as shown in
FIG. 3
, prior to growing a thinner second gate oxide
15
on the logic device areas L, it is necessary to remove the native oxide in the logic device areas using a wet etch. However, the exposure of the first gate oxide
13
to the wet etch makes it difficult to accurately control the thickness of the thicker gate oxide, composed of oxide layers
13
and
15
, over the memory device areas when the second oxidation step is performed.
Numerous methods of forming logic circuits with embedded memory devices having dual gate oxides have been reported in the literature. One method of making a dual-thickness gate oxide is described in U.S. Pat. No. 5,960,289 to Tsui et al. In Tsui's method a first gate oxide is deposited and a protection layer (Si
3
N
4
) is deposited. The two layers are then patterned to expose some of the device areas. The exposed device areas are oxidized to form a thin second gate oxide for high-performance circuits, while the first gate oxide and the protection layer serve as the thicker gate dielectric for the DRAM and the SRAM cells.
Sugaya in U.S. Pat. No. 4,945,068, teaches a method for forming a thick and thin dual-thickness gate oxide using only a single oxidation step. The method achieves the dual thickness by using an ion implant mask and implanting (injecting) nitrogen (N
2
) ions into some of the silicon substrate device areas while masking from implant other device areas. A thermal oxidation is performed in which the oxide grows slower on the N
2
implanted areas than in non-implanted device areas.
Ong in U.S. Pat. No. 5,880,041 describes a method for using high-pressure oxidation to grow a gate oxide on a silicon substrate. The high pressure increases the oxidation rate (Angstroms/minute) and decreases the oxidation time, which reduces the thermal budget.
Fang et al. in U.S. Pat. No. 5,668,035 describe a method for forming a dual gate oxide for memory with embedded logic technology. The method grows a first gate oxide over memory and logic device areas. Then a polysilicon layer is deposited and patterned to expose the first gate oxide over the logic device areas and to protect the first gate oxide over the memory device areas. The first gate oxide is removed by wet etch over the logic device areas and a thinner second gate oxide is grown over the logic device areas.
Matsuoka et al. in U.S. Pat. No. 5,926,741 describe a method for forming a gate dielectric layer without generation of a natural oxide film. The method involves cleaning the silicon wafer in an inert gas ambient and replacing the ambient gas with an oxidizing gas and applying heat to form the gate oxide on the wafer.
However, there is still a need in the semiconductor industry for fabricating dual-thickness gate oxides using a simple cost-effective process, while preventing native oxides from forming on device areas, as well as avoiding boron penetration in the thin gate oxides for P-channel FETs.
SUMMARY OF THE INVENTION
It is a principal object of the present invention to form dual gate oxides on a single integrated circuit chip for field effect transistors (FETs) for making a thin effective gate oxide for high-performance logic circuits and a thicker gate oxide for non-volatile memory and/or peripheral circuits.
It is another object of the invention to use a patterned thin silicon nitride (Si
3
N
4
) layer to form the thin gate oxide while concurrently forming the thicker gate oxide using a single oxidation step.
A further objective of this invention is to use a single oxidation step to reduce processing complexity and to improve product reliability.
The method for making this dual gate oxide using a patterned thin Si
3
N
4
layer for CMOS logic circuits and for non-volatile memory is now briefly described. The method begins by providing a semiconductor substrate. The substrate is typically a single-crystal silicon having a <100> crystallographic orientation. A field oxide is formed surrounding and electrically isolating CMOS logic device areas and memory device areas. Typically for these more advanced high-density integrated circuits, the field oxide is shallow trench isolation as commonly practiced in the industry. By the method of this invention the dual gate oxides are now formed by removing any native oxide that has inadvertently formed on the logic and memory device areas. Next a very thin blanket Si
3
N
4
layer (e.g., 10-20 Angstroms) is deposited on the substrate using chemical vapor deposition (CVD). Preferably the native oxide is removed in situ just prior to depositing the Si
3
N
4
layer to avoid reforming a native oxide. The Si
3
N
4
layer is then patterned using a photoresist mask and a hot phosphoric acid (H
3
PO
4
) etch. The Si
3
N
4
is patterned to leave portions over the logic device areas while exposing the surface of the memory and/or peripheral device areas. A key feature of this invention is that the photoresist mask used to pattern the Si
3
N
4
does not come in direct contact with a gate oxide, as in the prior art. Therefore the gate oxide and/or the substrate are not contaminated by the photoresist. Any second native oxide that has inadvertently formed on the memory device areas is now removed in a dilute hydrofluoric (HF) acid solution or an HF vapor etch, while essentially leaving unetched the patterned Si
3
N
4
over the logic device areas. The surface of the substrate is then subjected to a single oxidation step to form a thicker gate oxide (greater than or equal to 50 Angstroms) on the memory device areas, while concurrently converting the thin pattern
Jang Syun-Ming
Yu Mo-chiun
Ackerman Stephen B.
Le Dung Anh
Saile George O.
Taiwan Semiconductor Manufacturing Computer
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