Method for making dynamic random access memory cells using a nov

Details Method for making dynamic random access memory cells using a nov Method for making dynamic random access memory cells using a nov

1997-10-23

1999-07-20

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438631, H01L 218242

Patent

active

059267100

ABSTRACT:
A method is described for making an array of DRAM cells having increased capacitance. The method forms a planar insulating layer over FETs in an array of cells. Node contact openings are etched to each FET. A thick first polysilicon layer is deposited to fill the node contact openings and provide a planar polysilicon surface on the insulating layer. A thin silicon nitride layer is deposited on the first polysilicon layer, and both are patterned leaving portions having essentially vertical sidewalls over the contact openings. Polysilicon oxide sidewalls are formed on the first polysilicon layer by thermal oxidation. The nitride layer prevents oxidation of the top of the polysilicon. The nitride is removed and the polysilicon is selectively etched (recessed) leaving polysilicon oxide sidewalls. A second polysilicon layer is deposited over the oxide sidewalls and etched back to form inner and outer sidewall spacers. The oxide sidewalls and portions of the planar insulating layer are etched, lifting off the outer polysilicon sidewall spacers to provide a capacitor bottom electrode having vertical sidewalls. A thin capacitor dielectric layer is formed on the bottom electrodes and a third polysilicon layer is deposited and patterned to form the top electrodes and to complete the array of stacked capacitors on the DRAM device.

REFERENCES:
patent: 5399518 (1995-03-01), Sim et al.
patent: 5468670 (1995-11-01), Ryou
patent: 5545582 (1996-08-01), Roh
patent: 5604146 (1997-02-01), Tseng
patent: 5759888 (1998-06-01), Wang et al.
patent: 5792688 (1998-08-01), Tseng

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