Method for making dynamic random access memory cells having brus

Details Method for making dynamic random access memory cells having brus Method for making dynamic random access memory cells having brus

1998-04-24

2000-06-20

Chaudhuri, Olik

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438398, 257309, H01L 218242

Patent

active

060777435

ABSTRACT:
An array of DRAM cells having brush-shaped stacked capacitors with increased capacitance is achieved. A first planar insulating layer is formed having openings over the FET source/drain areas for node contacts. A doped first polysilicon layer and a silicide layer are deposited and patterned to form bit lines and concurrently form the capacitor node contacts in the openings. A planar second insulating layer is deposited with second openings aligned over the node contacts. A multilayer composed of a doped second polysilicon layer, an etch end-stop layer (silicide or undoped polysilicon), a thick doped third polysilicon layer, and a thin insulating layer is deposited and patterned to form the capacitor bottom electrodes. A thin hemispherical-shaped grain (HSG) fourth polysilicon layer is deposited and used as an etch mask to form a sieve-like mask in the third insulating layer on the top of the bottom electrode. The sieve-like mask is then used to anisotropicaly etch the bottom electrode to the etch-stop layer without overetch to form a brush-like electrode while retaining the HSG layer on the sidewalls of the bottom electrodes to increase capacitor area. An interelectrode dielectric layer and a doped fifth polysilicon layer are deposited and patterned to complete the improved stacked capacitors for the DRAM devices.

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Y.K. Jun. "The Fabrication and Electrical Properties of Modulated Stacked Capacitor for Advanced DRAM Applications", IEEE Electron Device Letters, vol. 13, No. 8, Aug. 1992, p. 430-432.

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