Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-26
2002-05-21
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S248000, C438S249000, C438S386000, C438S391000, C438S392000
Reexamination Certificate
active
06391706
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to an integrated circuit semiconductor device, and more particularly to a method for making improved deep trench capacitors for dynamic random access memory (DRAM) devices. The method uses a thicker pad silicon nitride (Si
3
N
4
) layer with a chemical-vapor-deposited glass layer as a hard mask for etching the deep trenches. This avoids overetching and damaging (faceting) the hard mask at the extreme edge of the wafer when the deep trenches are etched in the wafer. At a later processing step after completing the trench capacitors, the pad silicon nitride layer is used as a polish-back stop layer for making shallow trench isolation (STI). Due to the inherent properties of the chemical-mechanical polishing (CMP), the polish-back stop layer has reduced thickness at the center of the wafer (substrate) and is thicker at the wafer edge. To further improve process yield after CMP, the invention uses an additional patterned mask layer to protect the wafer center while exposing the silicon nitride stop layer at the wafer edge. The thicker portion of the pad Si
3
N
4
layer is partially removed at the water edge to form a more uniform pad Si
3
N
4
.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) devices are used for storing digital information on arrays of memory cells in the form of charge stored on capacitors. Each memory cell consists of a single access transistor and a single storage capacitor. The storage capacitors are formed either by etching deep trenches in the substrate in each cell area, commonly referred to as trench capacitors, or are formed over the access transistors in the cell areas by depositing and patterning conducting layers over the access transistors, and are commonly referred to as stacked capacitors. The capacitors make electrical contact to one of the two source/drain areas (node contacts) of each FET (access transistor), while bit lines make electrical contact to the other source/drain area of each FET. Read/write circuits, on the periphery of the DRAM chip, are used to store binary data by charging or discharging the storage capacitor via the bit lines, and the binary data is read (or sensed) by peripheral sense amplifiers, also via the bit lines. However, each capacitor must lie within an area about the size of the cell area in order to accommodate all the capacitors in the large array of cells used on the DRAM device.
As the number of memory cells increases on the DRAM chip and the cell areas decreases, it becomes increasingly difficult to fabricate the storage capacitors with reasonable surface area for maintaining sufficient capacitance (charge). For example, after the year 2000 the number of memory cells on a DRAM chip is expected to exceed several gigabits. Further, as the cell area decreases, the available area for the storage capacitor in each cell also decreases. This makes it difficult to maintain sufficient capacitance for storing charge to provide the necessary signal-to-noise ratios.
One method used in the semiconductor industry to overcome the above problems is to form DRAM devices with stacked capacitors or trench capacitors. However, the stacked capacitors, which are built on the chip surface, result in rough topography which makes subsequent processing difficult and requires leveling and planarizing techniques that can be expensive.
An alternative method for making an array of DRAM cells is by forming deep trench capacitors in the silicon substrate. The surface therefore remains essentially planar and available for wiring for the DRAM circuit. Also, by forming the storage capacitors in a trench etched in the silicon substrate, it is possible to leave the substrate surface free for the bit lines, thereby providing adequate separation between bit line and storage capacitor. This also allows memory cells to be built with smaller surface areas for future high-density DRAM arrays.
However, as the diameter of the trench decreases to sub-quarter-micrometer widths, it becomes necessary to significantly increase the trench depth. For example, for future gigabit DRAMs the aspect ratio (depth/width) of the trench can be greater than 35. Unfortunately, etching these narrow deep trenches in a silicon substrate can be difficult to achieve and can result in excessive erosion of the hard mask and lead to damage of the substrate surface. This problem is particularly exacerbated at the edge of the substrate (wafer), and the problem becomes more severe as the substrate diameter increases. To better appreciate this problem,
FIGS. 1 and 2
show schematic cross-sectional views replicating SEM cross-sectional views for two adjacent trenches of the multitude of trenches formed.
FIG. 1
shows a cross section of two adjacent trenches
2
formed in the substrate
10
away from the edge of the substrate, and
FIG. 2
shows a cross section of two adjacent trenches
2
formed at the edge of the substrate. Typically the trenches are made by forming a thin stress-release silicon oxide layer (not shown), and depositing a pad Si
3
N
4
layer
12
and a chemical-vapor-deposited silicon oxide layer
14
to form a hard-mask layer. The hard-mask layer (layers
12
and
14
) is then patterned using conventional photolithographic techniques and plasma etching to etch a multitude of openings for deep trenches. After stripping the photoresist, the hard mask is used to selectively etch deep trenches
2
in the substrate
10
, two of which are shown in FIG.
1
.
Although the Si
3
N
4
layer
12
is faceted at the point S, the trenches
2
in the silicon substrate
10
have essentially vertical sidewalls, and the trench openings replicate the hard-mask openings. However, during typical processing to deposit the hard-mask layer, the Si
3
N
4
is thinner at the edge of the substrate, and the plasma etching to form the trenches in the substrate generally etches faster at the substrate edge. This results in excessive faceting that damages the substrate at the edge and distorts the trench profile
2
, as shown at points S in FIG.
2
. In more severe cases of overetching, the etching of the array of closely spaced trenches can result in a series of silicon needle-like structures. In both cases, the overetch reduces the usable surface area on the substrate, thereby reducing product yield.
Another problem occurs later in the trench capacitor process in which the chemical-mechanical polishing (CMP) to form the shallow trench isolation results in non-uniform polish-back of the shallow trench film material and also results in non-uniform etching of the underlying pad Si
3
N
4
layer
12
. The graph in
FIG. 14
show the thickness profile of the pad Si
3
N
4
layer
12
as a function of distance from the center of the wafer to the edge. The y axis shows the Si
3
N
4
thickness, and the x axis is the distance from the center of a 200-millimeter diameter wafer. As can be seen the thickness of the Si
3
N
4
increases significantly due to the polishing loading effect as one approaches the edge of the wafer. The two curves in the graph (
FIG. 14
) represent the variation in the Si
3
N
4
thickness in Angstroms. Curve A shows the results for a new polishing pad, and curve B shows the results for the conventional process using a polishing pad after several passes. The results of the polishing show unacceptable (increased) variations in thickness as one approaches the edge of the wafer. Therefore, it is strongly desirable to improve the uniformity as indicated by the curve C in FIG.
14
.
Several methods of making deep-trench capacitors are described in the literature. For example, Golden et al. in U.S. Pat. No. 5,618,751 teach a method for making a deep trench using a photoresist fill and recess to simplify the process and improve repeatable capacitor uniformity from wafer to wafer. In U.S. Pat. No. 6,071,823 to Hung et al. a method is described for making a bottle-shaped etched deep trench for increased capacitance. Yoshida in U.S. Pat. No. 5,885,863 teaches a method for making a simple contact to burie
Chiu Sheng-Fen
Chung Jesse
Wang Hsiao-Lei
Wu Chao-Chueh
Ackerman Stephen B.
Chaudhari Chandra
ProMos Technologies Inc.
Saile George O.
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