Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-29
2001-03-27
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S283000, C438S297000
Reexamination Certificate
active
06207510
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor devices, and, more particularly, to a method for making an integrated circuit.
BACKGROUND OF THE INVENTION
As Complementary Metal Oxide Semiconductor (CMOS) technologies advance with smaller feature sizes and thinner gate oxides, power supply voltages have been scaled down to improve reliability and to conserve power. For MOS field effect transistors (MOSFETs), a thinner gate oxide corresponds to a faster device and to a lower voltage threshold. Even with operating voltages being reduced, some low voltage MOSFETs, which typically operate at 1.5 to 2.5 volts, must still interface with high voltage MOSFETs, which typically operate at 3.3 to 5 volts. There is also a need for high voltage MOSFETs to preform certain analog functions not easily performed at low voltage. Because MOSFETs can be designed to operate at different operating voltages for performing different functions, it is desirable for a semiconductor substrate to include different thicknesses of gate oxide layers to accommodate the different operating voltages.
Such a dual voltage semiconductor device is formed by growing two different gate oxide thicknesses. Thin gate oxides are grown for low voltage transistors, and thick gate oxides are grown for high voltage transistors. Furthermore, different gate oxide thicknesses require different doping levels under the gate oxide at the surface of the semiconductor substrate to obtain the correct transistor properties for the desired voltage threshold.
The extra processing steps needed to create a dual voltage semiconductor device may be performed by separately implanting high and low voltage active regions corresponding to the high and low voltage transistors to be formed therein. One approach is to mask off a portion of the semiconductor substrate to define the high voltage active regions. The high voltage active regions are defined by implanting impurities into the semiconductor substrate. This procedure typically requires three implantation steps. One for the well implant, one to suppress punch-through formation of the transistor, and a third to adjust a voltage threshold of the transistor. Once the high voltage active regions are defined, then the regions are masked off so that the additional implantation steps can be performed to define the low voltage active regions. Therefore, separately implanting high and low voltage active regions requires extra masking steps and repeated implantation steps to independently control definition of the high and low voltage transistors to be formed.
Instead of performing separate implantation steps for the high and low voltage active regions, another approach is to use a single mask to perform implantations that are common to both the high and low voltage active regions. This step avoids having to perform repeat implant steps. Common implantations include defining the wells and inhibiting or suppressing punch-through formation of the transistors. However, extra masks are required for performing the individual voltage threshold adjust implants for defining the particular thresholds of the high and low voltage transistors
The choice between using extra masks or performing repeated implantation steps for forming a desired dual voltage integrated circuit depends on the relative cost of photolithography processing versus the cost of performing implantation steps. Consequently, there is a continuing need to reduce processing costs in forming dual voltage integrated circuits, particularly through the reduction of masks and repeated implantation steps.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to provide a method for making an integrated circuit including high and low voltage transistors at a reduced processing cost.
It is another object of the present invention to provide a method for making an integrated circuit including high and low voltage transistors using a reduced number of masks and without performing repeated implantation steps
These and other advantages, features and objects in accordance with the present invention are provided by a method for making an integrated circuit including high and low voltage transistors comprising the steps of forming a plurality of spaced apart isolation regions in a substrate to define active regions therebetween, forming a first mask, and using the first mask for performing at least one implant in the active regions for defining high voltage active regions for the high voltage transistors. The method preferably further includes the steps of removing the first mask and forming a second mask, and using the second mask for performing only one implant for converting at least one high voltage active region into a low voltage active region for a low voltage transistor.
All of the implantations needed to define the high voltage transistors are thus performed throughout the active regions using the first mask. Consequently, this defines all of the active regions to be high voltage active regions. A separate adjustment implantation is then performed using the second mask to convert at least one of the high voltage active regions to a low voltage active region for the low voltage transistor. Because this adjustment implantation can be performed to convert at least one high voltage active region to a low voltage active region, only one additional mask is needed, and no repeated implantations are required. This advantageously reduces processing costs for making an integrated circuit including high and low voltage transistors.
The method also preferably includes the steps of forming gate dielectric layers on the high and low voltage active regions for corresponding high and low voltage transistors, and forming gates on the gate dielectric layers.
REFERENCES:
patent: 5403764 (1995-04-01), Yamamoto et al.
patent: 5903493 (1999-05-01), Lee
patent: 6030862 (2000-02-01), Kepler
patent: 6043128 (2000-03-01), Kamiya
Abeln Glenn C.
Ashton Robert Alan
Chaudhry Samir
Massengale Alan R.
Ning Jinghui
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Le Dung Anh
Lucent Technologies - Inc.
Nelms David
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