Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-01
2001-09-04
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S264000
Reexamination Certificate
active
06284608
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and more particularly to semiconductor on insulator devices.
BACKGROUND OF THE INVENTION
Integrated Circuits (IC) containing Semiconductor On Insulator (SOI) devices are becoming increasingly important due to their speed. An SOI device (i.e., transistor) is typically formed in a layer of semiconductor material overlaying an insulating layer formed in a semiconductor substrate.
A prior art SOI transistor includes a source region and a drain region which are separated from each other by a channel region. Both the source and drain regions are of the same conductivity type and are of opposite conductivity type to that of the body region. For example, when the body region is of a p-type material, the source and drain regions are of an n-type material. The source and drain regions typically have a higher dopant concentration level than the body region.
The transconductance of currently known SOI devices decreases as the supply voltage decreases. Therefore, a need exits for an SOI device which exhibits higher transconductance than SOI devices known in the prior art at low supply voltages.
SUMMARY OF THE INVENTION
An accumulation mode n-channel Silicon On Insulator (SOI) transistor, in accordance with one embodiment of the present invention, includes: an intrinsic silicon body region which contains two deep Boron and one shallow Phosphorous implants; source/drain regions each including Arsenic implant; p-type regions adjacent each of the source and drain regions, and disposed along the channel.
The following processing steps are carried out to make the SOI device, in accordance with one embodiment of the present invention. After forming a shallow trench isolation, the top silicon layer receives deep Boron and shallow Phosphorous implants through a thin layer of an insulating material (e.g., oxide). Thereafter, gate oxide is grown, polysilicon gate is formed and a zero-tilt Arsenic implant is made to form the source/drain regions of the device. After a rapid thermal anneal, a tilted channel implant delivers BF2 impurities through an insulating layer (e.g., oxide liner) to the channel, thus creating p-type regions adjacent each of the source and drain regions. Thereafter, a shallow phosphorous implant is delivered to the channel and through oxide spacers formed adjacent the polysilicon gate to form n-type regions near each of the source and drain regions. A deep Boron implant is then performed to prevent punch-through. Next, a pair of second oxide spacers are formed adjacent the first oxide spacers and the wafer is subsequently salicided using a conventional salicidation process.
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Krishnan Srinath
Krivakapic Zoran
Maszara Witold
Advanced Micro Devices , Inc.
Kwok, Esq. Edward C.
Nguyen Tuan H.
Schillinger Laura M
Skjerven Morrill & MacPherson LLP
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