Method for making a vertical MOS transistor with embedded gate

Details Method for making a vertical MOS transistor with embedded gate Method for making a vertical MOS transistor with embedded gate

2007-12-04

2010-02-23

Hu, Shouxiang (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000, C438S271000, C257SE21410, C257SE21409, C257SE21412

Reexamination Certificate

active

07666733

ABSTRACT:
According to the invention, a transistor of vertical MOS type is produced in which an insulating assembly (28) formed above the drain (26) comprises insulating zones (42, 44) either side of the drain; cavities extend under the insulating assembly, either side of the channel (69); the gate (77a,77b) is formed either side of this insulating assembly; and portions of the gate are located inside the cavities. The invention applies to microelectronics.

REFERENCES:
patent: 5136350 (1992-08-01), Itoh
patent: 5504359 (1996-04-01), Rodder
patent: 5739057 (1998-04-01), Wind et al.
patent: 6107660 (2000-08-01), Yang et al.
patent: 6518622 (2003-02-01), Chew et al.
patent: 6624032 (2003-09-01), Alavi et al.
patent: 197 46 901 (1999-05-01), None
patent: 2 103 879 (1983-02-01), None
patent: 97 48135 (1997-12-01), None

Affiliated with

Also associated with

Rating

Method for making a vertical MOS transistor with embedded gate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for making a vertical MOS transistor with embedded gate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making a vertical MOS transistor with embedded gate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4162986