Method for making a stacked DRAM capacitor

Details Method for making a stacked DRAM capacitor Method for making a stacked DRAM capacitor

1998-07-22

2000-07-18

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438398, H01L 218242

Patent

active

060906642

ABSTRACT:
A method of forming a capacitor for a stacked DRAM memory cell. A contact hole is formed in a dielectric stack of an interlayer dielectric, a first nitride layer, a high temperature oxide (HTO) layer, and a second nitride layer. An in-situ doped amorphous silicon segment is formed in and over the contact hole. The second nitride layer is removed and then a hemispherical grain (HSG) polysilicon layer is formed over the amorphous silicon segment. The HTO layer is removed and a capacitor dielectric layer is formed over the HSG polysilicon layer. Finally, a top conductive layer is formed over the capacitor dielectric layer.

REFERENCES:
patent: 5858838 (1999-01-01), Wang et al.
patent: 5874336 (1999-02-01), Cherng et al.

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