Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-02
2004-03-23
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S393000, C438S638000, C438S672000, C438S959000
Reexamination Certificate
active
06709918
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method for making semiconductor integrated circuits, and more particularly a method for making metal-insulator-metal (MIM) capacitors and concurrently making resistor structures compatible with a copper (Cu) metallization scheme requiring only a single additional masking step. This simplified method is designed to prevent via punchthrough to the top electrode. This novel method also retains the utilization of the capacitor dielectric layer as an etch-stop layer to prevent overetching the copper bottom plate that causes copper particle, and thereby avoiding additional processing steps. The MIM capacitors can be used in an integrated circuit as anti-fuse devices.
(2) Description of the Prior Art
Capacitors are used for various integrated circuit applications. For example, making metal-insulator-metal (MIM) capacitors can be used for mixed signal (analog/digital circuits) applications and radio frequency (RF) circuits, and can also serve as decoupling capacitors to provide improved voltage regulation and noise immunity for power distribution.
In previous generations of semiconductor technology, these capacitors are integrated into the semiconductor circuit when the semiconductor devices are formed on the substrate. For example, the one or two doped patterned polysilicon layers used to make the field effect transistors (FETS) and/or bipolar transistors can also be used to form the capacitors. Alternatively, the capacitors can be fabricated using the multilevels of interconnecting metal patterns (e.g., Al/Cu) used to wire up the individual semiconductor devices (FETs).
In recent years the AlCu metallization has been replaced with copper (Cu) to reduce significantly the resistivity of the conductive metal lines and thereby improve the RC (resistance×capacitance) delay time for improved circuit performance. By using Cu lines, the resistance in series with MIM capacitors is reduced resulting in a higher figure of merit Q (X
c
/R), where X
c
is the capacitor reactance expressed in ohms, and R is the resistance (ohms).
Several methods of making MIM capacitors are described in the literature. One method is described in the Interconnect Technology Conference 2000 Proceedings of the IEEE 2000, page 111, in a paper entitled “Single Mask Metal-Insulator-Metal (MIS) Capacitor with Copper Damascene Metallization for Sub-0.18 &mgr;m Mixed Mode Signal and System-on-a-Chip (SoC) Applications” by R. Liu et al., Lucent Technologies Bell Laboratories in which a Cu damascene process is used to form the bottom electrode and then a Si
3
N
4
dielectric is deposited as the capacitor dielectric and as a barrier layer. A conducting material such as TiN, AlCu/TiN, or Ti/TiN/AlCu/TiN is deposited and is patterned by selective etching to stop on the Si
3
N
4
layer to form the top electrode. The paper does not address forming a metal resistor or making contacts to the top electrode. In the Proceedings of the IEEE/IEDM 2000, page 153, a paper entitled “Integration of Thin Film MIM Capacitors and Resistors into Copper Metallization based RF-CMOS and Bi-CMOS Technologies” by P. Zurcher et al. of Motorola describes a method for making a MIM capacitor and a metal resistor using a Cu dual-damascene process and forming a bottom electrode of TaN, forming a Si
3
N
4
capacitor dielectric layer and a top electrode also formed from TaN. The bottom electrode TaN layer is also patterned to form resistors. A second damascene process is then used to make contacts to the capacitor top electrode and to the resistor and to the underlying metal layers. Other methods of forming MIM capacitors include a paper by M. Armacost et al. of IBM entitled “A High Reliability Metal Insulator Metal Capacitor for 0.18 &mgr;m Copper Technology” in the Proceedings of the IEEE/IEDM 2000, page 157, and in the Proceedings of the IEEE/IEDM 1999, page 849, R. Mahnkopf et al. of Infineon and IBM describe a method for making a MIM capacitor in a Cu dual-damascene metallization scheme in a paper entitled “‘System on a Chip’ Technology Platform for 0.18 &mgr;m Digital, Mixed Signal & eDRAM Applications.”
Several patents have been issued for making MIM capacitors. U.S. Pat. No. 6,117,747 to Shao et al. describes a method that utilizes an additional thin metal layer to form a bottom capacitor plate which extends over the edge of a Cu dual-damascene structure. Ma et al., U.S. Pat. No. 6,329,234 B1, describe a method for making a MIM capacitor structure and concurrently an inductor using a single photoresist mask for high-frequency mixed-signal Rf, CMOS applications compatible with a Cu dual-damascene process. U.S. Pat. No. 6,320,244 B1 to Alers et al. describes a method for integrating MIM capacitors with a Cu dual-damascene process. The capacitor is formed in a recess in an insulating layer over an underlying interconnect structure of the integrated circuit. Tu et al. in U.S. Pat. No. 6,271,084 B1 describe a method for making vertical MIM capacitors using a damascene process in which the vertical sidewalls of the capacitor are used to increase the capacitance.
There is still a need in the semiconductor industry to form metal-insulator-metal (MIM) capacitors with high capacitance while improving process yield and product reliability.
SUMMARY OF THE INVENTION
A principal object of the present invention is to fabricate a Metal-Insulator-Metal (MIM) capacitor and concurrently make a resistor structure compatible with a copper (Cu) metallization scheme, requiring only one additional masking step.
A second object of this invention is to avoid particle generation by patterning the top plate by etching down to and partially into an interelectrode dielectric layer thereby avoiding etching the Cu bottom plate.
A third objective of this invention is to use a Cu bottom plate to reduce series resistance and thereby improve the figure of merit Q (X
c
/R).
Still another objective is to provide an etch-stop layer on the capacitor top plate to prevent via punchthrough to the top plate when via holes are etched through an overlying insulating layer to the capacitor top plate.
A further objective is to incorporate the MIM capacitor into the circuit design to form an anti-fuse, which can then be shorted by applying a voltage between the capacitor plates that is greater than the dielectric breakdown voltage of the capacitor.
The present invention is a method for making improved MIM capacitors using one additional masking step and is compatible with concurrently making metal resistors. This novel process eliminates damage to the capacitor when making via holes through an insulating layer to the top plate of the capacitor. Since the bottom plate is formed from a low-resistance metal (Cu), the figure of merit Q (X
c
/R) is increased significantly. Although the method is described using a dual-damascene process, it should be understood that a single-damascene process can also be used.
In sugary the method of this invention begins by providing a semiconductor substrate having partially completed semiconductor circuits, such as FETs and the like, and includes at least one level of metal interconnections embedded in, and coplanar with a first insulating layer. A dual-damascene process is used to form concurrently the bottom plate of the capacitor integrated with the next level of interconnections. The dual-damascene process comprises forming a first etch-stop layer on the first insulating layer, depositing a second insulating layer, depositing a second etch-stop layer, depositing a third insulating layer. First and second recesses are formed in the third insulating layer to the second etch-stop layer. The first recesses are for capacitor bottom plates, and the second recesses are for metal lines. Next, first via holes are etched in the second etch-stop layer and in the second insulating layer exposed within the recesses to the first etch-stop layer. The second etch-stop layer is removed in the first via holes to the underlying metal interconnections. A conformal first barrier layer is
Chew Kok Wai
Chu Shao Fu Sanford
Ho Chaw Sing
Li Jian Xun
Ng Chit Hwei
Brewster William M.
Chartered Semiconductor Manufacturing Ltd.
Coleman W. David
Pike Rosemary L. S.
Saile George O.
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