Method for making a dual gate structure for CMOS device

Details Method for making a dual gate structure for CMOS device Method for making a dual gate structure for CMOS device

1999-06-25

2001-01-16

Bowers, Charles (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S176000, C438S157000, C257S369000, C257S072000

Reexamination Certificate

active

06174775

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to create a gate structure, for a complementary metal oxide semiconductor, (CMOS), device, comprised with a P type doped region, in a first region of the gate structure, and comprised with an N type doped region, in a second region of the gate structure.
(2) Description of the Related Art
The objective of increasing semiconductor device performance has been successfully addressed by the trend to micro-miniaturization, or the ability to fabricate semiconductor devices, using sub-micron features. However when using sub-micron features to fabricate a buried channel, P channel, or pMOS, type device, an undesirable, yield and reliability degrading, short channel effect, can result. Therefore the pMOS devices, in the CMOS cell, are now being fabricated as surface channel devices, similar to the N channel, or nMOS counterparts. However to avoid higher threshold, and operating voltages, encountered when using an N type, polysilicon gate structure, for the surface channel, pMOS device, a P doped gate structure is employed, resulting in a minimum work function, hence a lower threshold voltage. However to obtain the same threshold voltage benefits, the nMOS devices still have to be fabricated using N doped, gate structures. Thus the use of a continues dual gate structure, comprised of polysilicon, or polycide, (metal silicide-polysilicon), featuring P type doped regions, overlying subsequent pMOS channel regions, and N type doped regions, overlying subsequent nMOS channel regions, is used to traverse both the CMOS cell.
The use of polycide gate structure, improving performance as a result of lower word line resistance, can however present problems, when used as a component of a dual gate structure. The diffusion coefficient for dopants such as boron, phosphorous and arsenic, is about five orders of magnitude higher in metal silicide layers, than the diffusion coefficient for these same dopants in polysilicon. Therefore during subsequent hot process procedures, such as source/drain activation anneals, or the formation of self-aligned contact openings, and structures, dopants in the polysilicon component of the polycide gate structure, can enter the metal silicide component of the polycide gate structure, then quickly move laterally in the metal silicide, and perhaps diffuse into an underlying region of the polysilicon component, that has been doped with a dopant of the opposite type. This auto-doping phenomena can result in unwanted threshold voltages, for the subsequent CMOS devices.
This present invention will describe a process for forming a polycide, dual gate structure, however this invention will feature the use of an undoped polysilicon layer, placed between the underlying, dual doped, polysilicon component, and the overlying metal silicide layer. Therefore during subsequent process steps, performed at elevated temperatures, only slow, or no movement of dopants, into the undoped polysilicon layer occurs, avoiding the auto-doping phenomena, and thus allowing the designed and desired operating and threshold voltages, to be maintained. Prior art, such as Fujii et al, in U.S. Pat. No. 5,341,041, as well as Matsumoto in U.S. Pat. No. 5,877,535, describe processes for reducing auto-doping, in a dual gate structure, via use of pre-doping of the metal silicide component. However these prior arts do not describe the novel approach of using an undoped polysilicon layer, used to prevent dopants from the polysilicon component of a polycide, dual gate structure, from reaching the metal silicide component of the polycide structure, where it can initiate the unwanted auto-doping phenomena.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate CMOS devices, comprised of surface channel type, pMOS devices, and surface channel, nMOS devices.
It is another object of this invention to use a polycide, dual gate structure, comprised of an overlying metal silicide layer, and a dual doped polysilicon layer, with a first region of the dual doped polysilicon layer comprised with P type dopants, in the region in which the polycide, dual gate structure, overlays pMOS devices, and comprised with N type dopants, in a second region of the dual doped polysilicon layer, in region in which the polycide, dual gate structure overlays nMOS devices.
It is still another object of this invention to use an undoped polysilicon layer, located between the overlying metal silicide component, and the underlying dual doped polysilicon component of the polycide, dual gate structure.
In accordance with the present invention a method of fabricating a polycide, dual gate structure, for CMOS devices, comprised of surface channel type, nMOS, as well as surface channel pMOS devices, and featuring an undoped polysilicon layer, located between an overlying metal silicide component, and an underlying dual doped, polysilicon component of the polycide, dual gate structure, is described. A gate insulator layer is formed on the surface of a semiconductor substrate, with the semiconductor substrate comprised with an N well regions, in a region to be used for subsequent pMOS regions, and comprised with a P well regions, in a region to be used for subsequent nMOS regions. A polysilicon layer is deposited, and is doped P type, in areas in which the subsequent gate structure will overlay N well regions, or regions in which subsequent pMOS devices will be formed, and is doped N type, in areas in which the subsequent gate structure will overlay P well regions, or regions in which subsequent nMOS devices will be formed. After deposition of an undoped polysilicon layer, and of an overlying metal silicide layer, patterning procedures are employed to create a polycide, dual gate structure, comprised of an overlying metal silicide component, and of an underlying, dual doped polysilicon component, and featuring an undoped polysilicon component, located between the metal silicide, and dual doped polysilicon components. Formation of P type, lightly doped source/drain regions, in the pMOS regions, and formation of N type, lightly doped source/drain regions, in the nMOS regions, is followed by the formation of insulator spacers on the sides of the polycide, dual gate structure. Heavily doped N type, source/drain regions are next formed for the nMOS devices, followed by the formation of heavily doped, P type, devices, for the pMOS devices. Borderless, or self-aligned contact openings, are next formed, followed by the creation of self-aligned contact structures, located in the self-aligned contact openings, contacting the heavily doped source/drain regions, of the CMOS devices.


REFERENCES:
patent: 5341014 (1994-08-01), Fujii et al.
patent: 5342794 (1994-08-01), Wei
patent: 5355010 (1994-10-01), Fujii et al.
patent: 5528065 (1996-06-01), Battersby et al.
patent: 5640037 (1997-06-01), Blanchard
patent: 5736436 (1998-04-01), Matsumoto et al.
patent: 5877535 (1999-03-01), Matsumoto
patent: 5976925 (1999-11-01), Cheek et al.
patent: 6051459 (2000-04-01), Gardner et al.

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