Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-05
2002-03-12
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S248000, C438S243000
Reexamination Certificate
active
06355518
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to an integrated circuit semiconductor device, and more particularly to a method for making deep-trench capacitors with overlying vertical cylindrical transistors (FET) for dynamic random access memory (DRAM) devices to form a very dense array of memory cells.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) circuits are used in the electronics industry for storing information as binary data. The DRAM circuit formed on chips diced from semiconductor substrates consists of an array of memory cells, and includes peripheral circuits for randomly accessing the memory cells for storing and retrieving the digital information. The individual DRAM cell is composed of a single FET, commonly referred to as a pass transistor, and a single charge storage capacitor. The storage capacitor is usually formed in the semiconductor substrate as a trench capacitor, or alternatively, formed as a stacked capacitor over the FET and within the cell area.
In recent years the cell density has increased dramatically on the DRAM chip because of improvements in the semiconductor technologies, such as high-resolution photo-lithography and directional plasma etching. In future DRAM technology the number of memory cells on a DRAM chip, each storing a bit of information, is expected to exceed a gigabit in the next several years. As this cell density increases on the chip it is necessary to reduce the area of each cell to maintain a reasonable chip size and to improve the circuit performance.
Unfortunately, as the cell size decreases, it is necessary to reduce the storage capacitor size to restrict the capacitor to within a cell area. This results in decreased charge stored on the capacitor that makes it more difficult to detect during the read cycle because of the lower signal-to-noise ratio at the read sense amplifiers. These volatile storage cells also require more frequent refresh cycles to maintain sufficient charge on the capacitor. Therefore, there is a strong need in the electronics industry to increase the capacitance of the storage capacitor while reducing the cell area.
Of the two approaches, the stacked capacitor has received considerable interest in recent years because of the variety of ways that the capacitor electrodes can be formed in the vertical (third) dimension over the FET and within the cell area to increase capacitance while reducing the cell area. However, the rough topography on the stacked capacitor requires an additional planarizing step to planarize the substrate surface in order to make more reliable submicrometer feature size structures, and the planarizing is a costly process that can also degrade product yield.
Alternatively, the DRAM cells can be made using deep-trench capacitors. In this approach the FET devices are formed adjacent to the trench capacitors and this limits reduction in cell area size. However, when the deep trench is formed in the substrate, the top surface of the substrate remains relatively planar and is available for forming the electrical interconnections having submicrometer feature sizes.
Several methods of making DRAMs with deep-trench capacitors have been reported. For example, Arnold, U.S. Pat. No. 5,937,296, forms a vertical transistor where the gate electrode is formed in the upper portion of the trench and source/drains are formed in the substrate. U.S. Pat. No. 5,302,541 to Akazawa shows a vertical transistor over a trench capacitor in which the source/drains are formed in a second conductive type material in the trench by out-diffusing from doped insulating oxide layers. In U.S. Pat. No. 5,744,386 to Kenney a vertical transistor is formed in the trench with an epitaxy, a gate oxide and gate electrodes formed in the trench. Lim, U.S. Pat. No. 6,018,176, forms a vertical transistor on a silicon-on-insulator substrate with a stacked capacitor over the transistor. p However, as the number of memory cells on a DRAM device continues to increase, there is still a strong need in the semiconductor industry to reduce the memory cell area while maintaining sufficient capacitance while providing a low-cost manufacturing process.
SUMMARY OF THE INVENTION
A principal object of this invention is to provide a very dense array of memory cells on a DRAM chip by forming a deep-trench capacitor with a vertical cylindrical transistor aligned over the capacitor, while providing a cost-effective process.
It is another object of this invention to form the vertical cylindrical transistor by forming the FET channel in an opening in the word line and aligned over the deep-trench capacitor.
A further object of this invention is to form an array of bit lines that are orthogonal to the word lines and that are aligned over the openings that have the FET channels.
In accordance with the objectives of the present invention, a method and structure are described for making an array of DRAM cells having deep-trench capacitors and vertical field effect transistors aligned over the deep-trench capacitors to decrease the cell area and dramatically increase DRAM cell density.
The method for making this array of DRAM cells with vertical FETs over capacitors is now briefly described. The method consists of providing a semiconductor substrate, preferably a P
−
doped single-crystal silicon substrate. Conventional deep-trench capacitors are formed in the substrate. The deep-trench capacitors are formed by using a patterned CVD silicon oxide/silicon nitride hard mask and anisotropic plasma etching to etch deep trenches in the silicon substrate. A thin dielectric layer is formed in the deep trenches to form a capacitor interelectrode dielectric layer. Then the trenches are filled with a first poly-silicon to form the capacitor electrodes and that also serve as the node contacts for the capacitors. Next a shallow trench isolation (STI) is formed to surround and electrically isolate the array of deep trenches. The STI also forms other active device areas, such as the peripheral device areas on the DRAM chip. The STI is formed by first removing the CVD SiO
2
portion of the hard mask. Then a shallow-trench photoresist mask and plasma etching are used to pattern the Si
3
N
4
portion of the hard mask and to etch shallow trenches in the substrate. The shallow trenches are formed to extend partly inward over the edge of the deep-trench capacitors and to leave active device areas over the first polysilicon deep-trench capacitors. The STI is completed by depositing an insulating layer and polishing back. A gate isolation oxide remains after chemical-mechanical polishing (CMP) on the surface of the first polysilicon layer in the deep-trench capacitors. Next, an N doped second polysilicon layer having a cap insulating layer is deposited and patterned to form word lines that extend over the deep-trench capacitors. An insulating layer is deposited over the word lines and polished back to expose the cap insulating layer on the word lines and to provide a planar surface. One important feature of this invention is to etch an array of openings in the cap insulating layer, in the polysilicon word lines, and in the gate isolation oxide. The openings are aligned over the first polysilicon (capacitor electrode) in the deep-trench capacitors. The source contacts for the vertical transistors are formed in the first polysilicon layer exposed in the openings by ion implantation. A gate oxide is formed on the sidewalls of the polysilicon word lines in the openings, followed by a bottom oxide etch using a directional plasma etch. Then a P doped third polysilicon layer is deposited sufficiently thick to fill the openings, and is polished back to the insulating layer to form FET channel cylinders. The drain contacts for the vertical transistors are formed in the top surface of the P doped third polysilicon layer exposed in the openings by ion implanting an N type dopant. An N doped fourth polysilicon layer is deposited and patterned to form an array of bit lines, that are orthogonal to the word lines, over the openi
Hsiao Chia-shun
Wu Chao-chueh
Ackerman Stephen B.
Fourson George
Pham Thanh
ProMos Technologies Inc.
Saile George O.
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