Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-07
2002-06-11
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S396000
Reexamination Certificate
active
06403416
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of dynamic random access memory (DRAM) devices, and more particularly to a method for fabricating stacked storage capacitors with increased capacitance for DRAM cells. The method allows for greater misalignment tolerances during processing, and therefore provides a larger process window. A minimal number of additional process steps is required over the more conventional capacitor process to minimize manufacturing cost, and is easily integrated into the DRAM process.
(2) Description of the Prior Art
Ultra Large Scale Integration (ULSI) technologies have dramatically increased the circuit density on the semiconductor chip. This increase in density is due in part to advances in high-resolution photolithography and anisotropic plasma etching in which the directional ion etching results in essentially bias-free replication of the photoresist image in the underlying patterned layers, such as in polysilicon and insulating oxide layers and the like.
One such circuit type where this high-resolution processing is of particular importance is the dynamic random access memory (DRAM) circuit. This DRAM circuit is used extensively in the electronics industry, and particularly in the computer industry for electrical data storage. The DRAM circuit consists of an array of individual memory cells, each cell consisting of a single access transistor, usually a field effect transistor (FET), and a single storage capacitor. Information is stored on the cell as charge on the capacitor, which represents a unit of data (bit), and is accessed by read/write circuits on the periphery of the DRAM chip.
There are numerous methods reported in the literature for making DRAM circuits with stacked capacitors that increase capacitance. For example, Kirsch, in U.S. Pat. No. 5,266,512, teaches a method for making a nested surface capacitor to improve memory cell density, while Sim et al., U.S. Pat. No. 5,399,518, describe a method for multiple walled capacitor to also increase capacitance and improve memory cell density. Liaw et al., U.S. Pat. No. 5,712,202, also teach a method for making a double or triple or higher walled-cylindrical capacitor of a semiconductor memory device. Roh, in U.S. Pat. No. 5,545,582, also teaches a method for making a device capacitor to increase capacitance.
However, in recent years the price of DRAM chips has dropped dramatically. Therefore there is a strong need to make a simple DRAM chip that is manufacturing cost effective.
However, the above patents do not address the problem when alignment tolerances become critical with reduced feature sizes, and misalignment problems can occur.
One method of making a simple low-cost DRAM capacitor by the prior art is depicted in
FIGS. 1 through 4
. To achieve a high density of memory cells on a DRAM chip is to form a capacitor node contact to one of the source/drain areas of the FET in each of the memory cells, and then to form a bottom electrode aligned over the node contact. In the next generation of semiconductor technology, the minimum feature sizes will be 0.25 micrometers or less. At these feature sizes, misalignment of the bottom electrode to the node contact can result in processing and reliability problems. The problem is best illustrated in the prior art depicted in
FIGS. 1 through 4
.
FIG. 1
shows a typical memory cell area on a substrate
10
surrounded and electrically isolated by field oxide regions
12
, and having a silicon oxide (SiO
2
) first insulating layer
20
and a silicon nitride (Si
3
N
4
) etch-stop layer
22
. A patterned photoresist mask (not shown) and plasma etching are used to etch first openings
1
in layers
22
and
20
for node contacts. A doped first polysilicon layer
24
is deposited and etched back to form the capacitor node contact
24
in opening
1
. Because of variations in etch rate uniformities across the substrate, and because of nonuniformity in the polysilicon deposition, it is necessary to overetch for forming the polysilicon plugs for the node contacts to ensure that all the polysilicon is removed from the surface of the etch-stop layer
22
. This results in recessed polysilicon plugs that expose the sidewalls of the first insulating layer
20
. A disposable second insulating layer
26
is deposited, and a second photoresist mask
28
and plasma etching are used to etch second openings
2
in layer
26
for forming the capacitor bottom electrodes, as shown in FIG.
1
.
Referring to
FIG. 2
, a conformal second polysilicon layer
30
is deposited and, as shown in
FIG. 3
, is polished back to form the capacitor bottom electrode
30
. The second insulating layer
26
is then removed to leave portions of the second polysilicon layer
30
to form capacitor bottom electrodes.
However, as shown in
FIG. 4
, when the photoresist
28
for making the second opening
2
is misaligned, the first insulating layer
20
in the sidewalls at point A of the node contact opening
1
are exposed to the wet etch (hydrofluoric acid) that is used to remove the second insulating layer
26
. The erosion of the first insulating layer
20
results in unreliable DRAM devices.
One method of circumventing the misalignment problem is described by Wang et al., U.S. Pat. No. 5,759,892, in which polysilicon sidewall spacers are formed in the node contact openings over the polysilicon plug. This prevents unwanted etching of the underlying insulating layer during processing when the capacitor bottom electrode is misaligned over the polysilicon plug, but this method does not further increase the capacitance over the other prior art.
Therefore, there is still a need to make DRAM device with increased capacitance using a simple cost-effective process that does not significantly increase the DRAM price.
SUMMARY OF THE INVENTION
A principal object of this present invention is to provide a method for making improved double-cylinder-shaped stacked capacitors for DRAM memory cells having increased capacitance.
It is another object of this invention to provide a method that is less susceptible to underlying silicon oxide damage over the device areas during misalignment of a photoresist mask.
Still another object of this invention is to provide a process for making a capacitor structure that is easily integrated into the DRAM cell process with minimal increase in processing complexity and manufacturing cost.
The invention begins by providing a semiconductor substrate (wafer) composed of single crystalline silicon. The details for the semiconductor devices in the substrate are not described in detail since they are not essential to understanding the invention. But typically the memory cells on a substrate for DRAM circuits have device areas surrounded and electrically isolated by field oxide (FOX) regions, and semiconductor devices for the memory devices are typically field effect transistors (FETs). The double-cylinder-shape storage capacitor, by the method of this invention, is then formed over each of the memory cell areas and electrically contacts (node contacts) one of the two source/drain areas of each FET.
Continuing with the process, a first insulating layer is deposited over the device areas on the substrate, and is planarized, for example by chemical-mechanical polishing. The first insulating layer is a silicon oxide (SiO
2
) or a doped oxide such as a borophosphosilicate glass (BPSG). A first silicon nitride (Si
3
N
4
) layer is deposited as an etch-stop layer on the first SiO
2
insulating layer. Contact openings for capacitor node contacts are etched in the first Si
3
N
4
layer and in the first insulating layer to the device areas. A conformal conductively doped first polysilicon layer is deposited to a thickness sufficient to fill the contact openings and to form an essentially planar surface over the contact openings. A second insulating layer composed of SiO
2
is deposited on the planar surface of the first polysilicon layer. A photoresist mask and anisotropic plasma etching are used to pattern the second insulatin
Chiang Wen-Chuan
Huang Kuo Ching
Lee Yu-Hua
Wu James (Cheng-Ming)
Ackerman Stephen B.
Estrada Michelle
Fourson George
Saile George O.
Taiwan Semiconductor Manufacturing Company
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