Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-05-11
2002-04-02
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S703000, C438S706000, C438S723000, C438S724000
Reexamination Certificate
active
06365524
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a trench process, and more particularly relates to a method for making a concave bottom oxide within a trench.
BACKGROUND OF THE INVENTION
A conventional trench process usually begins with the defining of the hard mask overlying the semiconductor substrate to form an opening exposing the surface of the semiconductor substrate. Then, the exposed semiconductor substrate within the opening is removed by means of wet- or dry-etching to form a trench. Subsequently, a silicon dioxide is formed overlying the side-walls and the bottom of the trench by means of thermal oxidation to oxidize a portion of the semiconductor substrate. However, the edge and the bottom of the trench could be rounder, thereby avoiding weak points in the edge of the trench, which results in leakage current.
Since the method described above comprises a thermal oxidation, the edge of resultant trench usually has so called “Bird's Beaks”. Moreover, it is hard to well control the thickness of the silicon dioxide during the thermal oxidation process. Also, the leakage current will be apparent when the bottom oxide within the trench is too thick. Therefore, it is necessary to develop a novel method for making a concave bottom oxide within a trench to overcome the drawback of the above conventional trench method.
The process of the above conventional trench method is illustrated in detail in FIGS.
1
A~
1
C and
2
A~
2
C.
CONVENTIONAL EXAMPLE 1
First, referring to
FIG. 1A
, a semiconductor substrate
100
, such as a silicon substrate, is provided. Then, a pad oxide
110
(e.g. a silicon dioxide layer) and a hard mask layer
120
(e.g. a nitride layer) are formed on the semiconductor substrate
100
in sequence. Then, photolithography procedures and etching techniques are applied to define the nitride
120
and the pad oxide layer
110
to form an opening
130
exposing the surface of the semiconductor substrate
100
.
Next, referring to
FIG. 1B
, using the hard mask layer
120
and the pad oxide layer
110
as a mask, the exposed semiconductor substrate
100
within the opening
130
is removed by means of wet-etching, thereby a V-trench
140
is formed.
Then, referring to
FIG. 1C
, a thermal oxidation process is applied to oxidize a portion of the exposed semiconductor substrate
100
of the V-trench
140
, thus a trench
150
with an overlying silicon dioxide layer
110
′ is formed.
Because the trench is defined by means of wet-etching, a V-trench is produced instead of a trench with a more vertical profile. In addition, the silicon dioxide layer
110
′ is formed by means of thermal oxidation, thereby the “Bird's beak” is apparent in the edges of result trench
150
.
CONVENTIONAL EXAMPLE 2
First, referring to
FIG. 2A
, a semiconductor substrate
200
, such as a silicon substrate, is provided. Then, a pad oxide
210
(e.g. a silicon dioxide layer) and a hard mask layer
220
(e.g. a nitride layer) are formed on the semiconductor substrate
200
in sequence. Then, photolithography procedures and etching techniques are applied to define the nitride
220
and the pad oxide layer
210
to form an opening
230
exposing the surface of the semiconductor substrate
200
.
Next, referring to
FIG. 2B
, using the hard mask layer
220
and the pad oxide layer
210
as a mask, the exposed semiconductor substrate
200
within the opening
230
is removed by means of dry-etching, thereby a U-trench
240
is formed.
Next, referring to
FIG. 2C
, a thermal oxidation process is applied to oxidize a portion of the exposed semiconductor substrate
200
of the U-trench
240
, thus a trench
250
with an overlying silicon dioxide layer
210
′ is formed.
It is noted that the trench is defined by means of dry-etching, thereby a trench with a more vertical profile can be obtained. However, the silicon dioxide layer
210
′ is still formed by means of thermal oxidation in order to produce a trench
250
with a rounder bottom, thereby the “Bird's beak” is still apparent in the edges of trench
250
.
In order to address the drawback of the conventional trench process described above, it is necessary to develop a novel trench process to make a concave bottom oxide within a trench.
SUMMARY OF THE INVENTION
In order to address the drawback of the conventional trench process described above, this invention discloses a method for making a concave bottom oxide within a trench.
The feature of the invention is to provide a method for making a concave bottom oxide within a trench, the steps comprising: providing a semiconductor substrate; forming an insulating layer on the semiconductor substrate; defining the insulating layer to form an opening exposing the surface of the semiconductor substrate; dry-etching the exposed semiconductor substrate within the opening by using the first insulating layer as an etching mask to form a trench; depositing a first oxide layer conformably over the insulating layer, the side-walls and the bottom of the trench; depositing a second oxide layer on the first oxide layer and filling-up the trench surrounded by the first oxide layer; annealing to densify the first and second oxide layers; etching-back the first and second oxide layer to remove the portion overlying the first insulating layer, and forming a spacer consisting of the residual first oxide layer on the side-walls of the trench, and a concave bottom oxide consisting of the first and second oxide layers on the bottom of the trench.
In the method according to this invention described, the insulating layer comprises a pad oxide layer and a nitride layer. The nitride layer consists of silicon nitride or silicon oxynitride. The first oxide layer is formed by means of CVD using O
3
/TEOS as reactants, and the ratio of O
3
/TEOS is less than 16. The second oxide layer is formed by means of CVD using O
3
/TEOS as reactant, and the ratio of O
3
/TEOS is more than 16. The etching-back step is applied by means of wet-etching. The wet-etching step is performed by using 5% HF as an etchant.
Other features and advantages of the invention will be apparent from the following detailed description, and from the claims.
REFERENCES:
patent: 5719085 (1998-02-01), Moon et al.
patent: 5786262 (1998-07-01), Jang et al.
patent: 5801082 (1998-09-01), Tseng
patent: 5858858 (1999-01-01), Park et al.
Chang Yen-Rong
Chen Chien-Hung
Chen Chung-Yih
Lin Jerry C. S.
Chou Chien-Wei (Chris)
Mosel Vitelic Inc.
Oppenheimer Wolff & Donnelly LLP
Umez-Eronini Lynette T.
Utech Benjamin L.
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