Method for low k dielectric deposition

Details Method for low k dielectric deposition Method for low k dielectric deposition

2003-05-08

2004-06-22

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

Reexamination Certificate

active

06753269

ABSTRACT:

BACKGROUND OF THE INVENTION
The present disclosure relates generally to the fabrication of semiconductor devices, and more particularly, to a method and process for depositing dielectric layers on a substrate.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 .mu.m and even 90 nm feature sizes.
In the process of reducing the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and insulators having low dielectric constants (k.ltoreq.4.0) to reduce the capacitive coupling between adjacent metal lines. A conductive material of interest is copper which can be deposited in submicron features by electrochemical deposition. Dielectric materials of interest are silicon oxides that contain carbon. Combination of silicon oxide materials and copper has led to new deposition methods for preparing vertical and horizontal interconnects since copper is not easily etched to form metal lines. Such methods include damascene methods depositing vertical and horizontal interconnects wherein one or more dielectric materials are deposited and etched to form the vertical and horizontal interconnects that are filled with the conductive material.
Dielectric layers can be deposited, etched and filled with metal in multiple steps. Preferred methods for depositing dielectric layers include damascene methods where lines/trenches are filled concurrently with vias/contacts. In a “counter-bore” scheme, a series of dielectric layers are deposited on a substrate, then vertical interconnects such as vias/contacts are etched through all of the layers and horizontal interconnects such as lines/trenches are etched through the top layers. A conductive material is then deposited in both the vertical and horizontal interconnects.
Because the selectivity of etch processes for conventional low k dielectric layers is typically less than 3:1, etch stop layers are needed to provide the desired etch selectivity. The etch stop layers provide uniformity in the depth of horizontal interconnects across the surface of the substrate. The etch stop layers farther reduce micro-trenching such that the bottom of horizontal interconnects are flat instead of deeper at outside edges. The etch stop layers further reduce faceting or fencing of previously etched vertical interconnects during etching of horizontal interconnects, wherein the edge between the bottom of the horizontal interconnects and the side walls of the vertical interconnects are sharp instead of either rounded (i.e., faceted) or raised (i.e., fenced) depending on whether the side walls of the vertical interconnects are exposed to etch gases or shielded from etch gases.
Conventional etch stop layers provide the benefits just described for damascene applications, but typically have dielectric constants that are substantially greater than 4. For example, silicon nitride has a dielectric constant of about 7, and deposition of such an etch stop layer on a low k dielectric layer results in a substantially increased dielectric constant for the combined layers. It has also been discovered that silicon nitride may significantly increase the capacitive coupling between interconnect lines, even when an otherwise low k dielectric material is used as the primary insulator. This may lead to crosstalk and/or resistance-capacitance (RC) delay that degrades the overall performance of the device.
What is needed is a process to form an intermediate trench layer without forming an etch stop layer in a low k material environment during semiconductor processing.
SUMMARY OF THE INVENTION
The present disclosure provides a method for forming an intermediate trench layer through low k dielectric material deposition in a damascene process for manufacturing semiconductor devices. After depositing a low k dielectric material block, a curing process is applied to the low k dielectric material block for a predetermined curing time period, wherein after the curing time period, the low k dielectric material block forms a first and second low k dielectric layers so as to make the first low k dielectric layer an intermediate trench layer, thereby eliminating the need of an etch stop layer.
The intermediate trench layer has a higher density than the second layer of the low k dielectric material. This property satisfies the needs to control future etch process, thus eliminating the need of the using an etch stop layer between the two low k dielectric layers and simplifying the entire low k material deposition process both in terms of processing time and cost. It provides a larger etch window about trench depth and profile control. And since the formation of both layers all will happen in one reaction chamber, it reduces the both the process time and costs. In addition, the increased density of the top layer low k material also enhances the material mechanical property.


REFERENCES:
patent: 5785789 (1998-07-01), Gagnon et al.
patent: 6340435 (2002-01-01), Bjorkman et al.
patent: 6537908 (2003-03-01), Fornof et al.

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