Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2006-02-21
2006-02-21
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S530000, C438S550000
Reexamination Certificate
active
07001832
ABSTRACT:
A method for limiting slip lines in a semiconductor substrate including a support layer and a useful semiconductor layer that is transferred to the support layer. The method includes precipitating at least a portion of interstitial oxygen in the support layer by a series of heat treatments conducted after bonding of the useful semiconductor layer to the support layer. The heat treatments occur at a temperature and a time sufficient to reduce the generation of slip lines therein.
REFERENCES:
patent: 4958061 (1990-09-01), Wakabayashi et al.
patent: 5985678 (1999-11-01), Kiyama
patent: 6127288 (2000-10-01), Kiyama
patent: 6184498 (2001-02-01), Kiyama
patent: 6235543 (2001-05-01), Kiyama
patent: 6274439 (2001-08-01), Ito
patent: 6544656 (2003-04-01), Abe et al.
patent: 2004/0171257 (2004-09-01), Neyret et al.
patent: 04168764 (1992-06-01), None
patent: 8236737 (1992-11-01), None
patent: WO 01/15215 (2001-03-01), None
Dang Phuc T.
S.O.I.Tec Silicon on Insulator Technologies S.A.
Winston & Strawn LLP
LandOfFree
Method for limiting slip lines in a semiconductor substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for limiting slip lines in a semiconductor substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for limiting slip lines in a semiconductor substrate will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3642596