Method for LDMOS transistor with thick copper interconnect

Details Method for LDMOS transistor with thick copper interconnect Method for LDMOS transistor with thick copper interconnect

2000-05-08

2002-04-16

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S316000

Reexamination Certificate

active

06372586

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to programmable integrated circuits utilizing lateral double diffused MOS technology, to the fabrication of LDMOS transistors, and specifically to the application of linear geometry lateral DMOS cells and circuits to transistors and integrated circuits for power applications, circuits and systems.
2. Description of the Related Art
In producing integrated circuits for power applications it is typical to use a process utilizing a lateral double diffused MOS (hereinafter LDMOS) technology. Devices are often designed using a plurality of lateral diffusions which are then coupled together to make a single large current capacity device.
In the prior art, single and double level metallization schemes are used to make the connections between the various diffusions and thereby form the large devices required for power circuits. Because the lengths of the metal runs are quite long, current distribution tends to become nonuniform across the devices. As a further consequence, debiasing also occurs along the metal lengths, which means different areas of the device are operating at different potentials. Non-uniform operation of the device results from this metal debiasing and the various diffused areas switch at different instants causing nonuniform current distribution.
Although the conventional two level metallization schemes of the prior art can be optimized to reduce the current debiasing problems, for fabricating large devices carrying large current loads the problems with debiasing remain. One approach to a two metal interconnection scheme for an LDMOS power device composed of many diffusion stripes is described in a co-pending U.S. patent application entitled “A Method for Current Ballasting and Busing over Active Device Area Using a Multi-Level Conductor Process”, U.S. application Ser. No. 07/850,601, assigned to Texas Instruments Incorporated. Although the techniques and structures for placing the contacts and vias in a two level metal interconnection scheme described in this earlier patent application will reduce the debiasing effects as much as possible using conventional metallization techniques, the problems persist for large transistors having long interconnect metal lengths.
In a LDMOS device formed from a plurality of diffusions coupled together using first and second levels of metal, the source and drain diffusions are alternating stripes. The source and drain diffusions are covered with, and in electrical contact with, stripes of the first metal layer, which is typically aluminum having a thickness of up to 1 micron. The first level metal is then covered with an isolation oxide. The second level metal is then used to form source and drain bus lines, each running over many of the source and drain diffusions, and each selectively coupling many of the first level metal stripes to a single bus through the use of contacts cut through the isolation oxide. This second level of metal can have a thickness of up to 3 to 4 microns. This system of interconnect is completely described in the active area bussing patent.
In the prior art LDMOS structures, the second level of metal looks like a resistor in series with the source or drain bond pad and the parallel devices. The amount of resistance provided by the metal interconnection is critical to the performance of the device because the critical parameter for performance, Rdson, is directly proportional to this resistance. For optimal performance of the completed device it is therefore desirable to minimize the metal resistance.
Modeling techniques have been used to show that for an exemplary LDMOS transistor comprised of 11 paralleled sections, each section having up to 150 diffusion stripes, coupled together using standard 1 micron first level metal and 3 micron aluminum for metal two in a conventional metal system with thicknesses as mentioned, the metal component of the critical Rdson resistance is as great as 63% of the total Rdson. This 63% contribution to the Rdson resistance is from the metal itself and the debiasing effects caused by the metal. Because of the metal resistance a large area of silicon is needed to lower the total Rdson of the device.
Other problems with the conventional methodology are also significant. Because the aluminum metallization scheme provides a somewhat resistive path for the current running along the diffusion stripes, there is an increase in the source voltage as measured from the end closest to the source buss to the other end of the diffusion. In an LDMOS transistor structure, this debiasing effect is of great concern because of the importance of the critical voltage Vgs. As the source voltage increases along the metal run, the voltage Vgs is reduced. As a result, in areas farther from the source pad there is nonuniform operation. As the source potential rises for a given gate voltage Vg, Vgs drops, the transistor segments receive less drive, and the overall device Rdson increases. The non-uniform current distribution due to non-uniform operation of the sections of the LDMOS device also leads to safe operating area problems, in the form of reducing the safe operating area of the device. In a condition where the gate voltage Vg is low, these problems become even greater, and device operation becomes marginal earlier than desired because the effective voltage Vgs is being significantly reduced in regions of high source debiasing. Drain debiasing is a problem also in that the drain potential drops across the device and the available design drive potential is not evenly distributed.
Additional problems arise due to the electromigration current density rules required with conventional metallization systems. Each of the sections of the LDMOS device is covered with a second level bus for the source and another for the drain. These busses are coupled together at the ends of the device. To meet the safe operating requirements using conventional metallization schemes, the busses at the ends of the device have to be made wider and wider as more sections are added, consuming proportionally more and more non-active device area to achieve larger devices.
Further problems arise as higher current capacity devices are designed using the prior art techniques. The nonuniformity of current distribution associated with debiasing can lead to so called “hot spots”, areas where localized current exceeds the thermal power limits of the device, and premature failure locations are the result. These premature failures further result in lower peak current capacity ratings for the devices and a reduced safe operating area rating. A need for an improved method for designing lateral power devices which enhances uniform current distribution and device operating efficiency, eliminating current crowding and electromigration concerns, and providing reduced Rdson performance, thus exists.
SUMMARY OF THE INVENTION
Generally, and in one form of the invention, a structure and method for designing a high current capacity LDMOS transistor device is provided using a lateral DMOS process, the device having a plurality of drain and source diffusions which are rectilinear in shape and laid out in rows. The individual source and drain diffusions are then covered with a first level metal using a conventional metal layer, then a second level of metal is deposited perpendicular to the first level metal fingers. The second level of metal forms source and drain busses which make selective contact to the plurality of source and drain diffusions using vias. A third level of metal is then deposited over the second level metal pattern using a thick conductive layer to form shorting busses. This third level is a low resistance material such as copper and is plated onto the device. The third level of metal is thick enough to greatly reduce the resistance of the metallization pattern and thereby reduce the Rdson resistance of the device. Further, current distribution and debiasing problems are greatly reduced. The need to be concerned with electromigration and current

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