Method for layout of random via arrays in the presence of...

Details Method for layout of random via arrays in the presence of... Method for layout of random via arrays in the presence of...

2008-08-04

2011-11-01

Whitmore, Stacy (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Design of semiconductor mask or reticle

Layout generation

C378S034000

Reexamination Certificate

active

08051391

ABSTRACT:
Exemplary embodiments provide a method for laying out an integrated circuit (“IC”) design and the IC design layout. In one embodiment, the IC design layout can include a first feature placed on a first intersecting point of a grid. The placed first feature can define a local grid area. The local grid area can further include a plurality of local intersecting points having an outer perimeter spaced from any outermost local intersecting point in a spacing ranging from a length of a grid side to a length of a grid diagonal of a grid unit. A second feature can either be restrictively placed on any local intersecting point of the local grid area, or be randomly placed on any location outside the outer perimeter of the local grid area.

REFERENCES:
patent: 2005/0142454 (2005-06-01), Fujimoto et al.
patent: 2006/0036977 (2006-02-01), Cohn et al.
patent: 2008/0086712 (2008-04-01), Fujimoto
patent: 2010/0185997 (2010-07-01), Allen et al.

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