Method for isolation layer for a vertical DRAM

Details Method for isolation layer for a vertical DRAM Method for isolation layer for a vertical DRAM

2006-07-11

2006-07-11

Tran, Mai-Huong (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S268000, C438S270000, C438S282000

Reexamination Certificate

active

07074700

ABSTRACT:
A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.

REFERENCES:
patent: 6930004 (2005-08-01), Wang et al.
patent: 439268 (2001-06-01), None

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