Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2007-06-28
2009-11-17
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S513000, C257SE21435
Reexamination Certificate
active
07618883
ABSTRACT:
A method for introducing impurities includes a step for forming an amorphous layer at a surface of a semiconductor substrate, and a step for forming a shallow impurity-introducing layer at the semiconductor substrate which has been made amorphous, and an apparatus used therefore. Particularly, the step for forming the amorphous layer is a step for irradiating plasma to the surface of the semiconductor substrate, and the step for forming the shallow impurity-introducing layer is a step for introducing impurities into the surface which has been made amorphous.
REFERENCES:
patent: 5407845 (1995-04-01), Nasu et al.
patent: 5561072 (1996-10-01), Saito
patent: 5892235 (1999-04-01), Yamazaki et al.
patent: 5897346 (1999-04-01), Yamaguchi et al.
patent: 5915196 (1999-06-01), Mineji
patent: 5956581 (1999-09-01), Yamazaki et al.
patent: 5969398 (1999-10-01), Murakami
patent: 6013332 (2000-01-01), Goto et al.
patent: 6025252 (2000-02-01), Shindo
patent: 6030863 (2000-02-01), Chang et al.
patent: 6037204 (2000-03-01), Chang et al.
patent: 6051482 (2000-04-01), Yang
patent: 6153524 (2000-11-01), Henley et al.
patent: 6159810 (2000-12-01), Yang
patent: 6218249 (2001-04-01), Maa et al.
patent: 6465727 (2002-10-01), Maruyama et al.
patent: 6583018 (2003-06-01), Matsunaga et al.
patent: 6653699 (2003-11-01), Yang
patent: 6713819 (2004-03-01), En et al.
patent: 6893907 (2005-05-01), Maydan et al.
patent: 2001/0025999 (2001-10-01), Suguro
patent: 2001/0039107 (2001-11-01), Suguro
patent: 2001/0048115 (2001-12-01), Yamazaki et al.
patent: 2002/0006689 (2002-01-01), Miyasaka
patent: 2002/0070382 (2002-06-01), Yamazaki et al.
patent: 2002/0112951 (2002-08-01), Fan
patent: 2003/0027393 (2003-02-01), Suguro
patent: 2003/0107036 (2003-06-01), Yamazaki et al.
patent: 2003/0193066 (2003-10-01), Ito et al.
patent: 2003/0211670 (2003-11-01), Downey
patent: 2003/0211713 (2003-11-01), Suguro et al.
patent: 2004/0166612 (2004-08-01), Maydan et al.
patent: 2004/1023528 (2004-11-01), DOWNEY et al.
patent: 2004/0241967 (2004-12-01), Yamazaki et al.
patent: 2005/0227463 (2005-10-01), Ito et al.
patent: 2005/0277273 (2005-12-01), Sasaki et al.
patent: 2006/0205192 (2006-09-01), Walther et al.
patent: 2006/0264051 (2006-11-01), Thibaut
patent: 2007/1025446 (2007-11-01), Sasaki et al.
patent: 1 648 023 (2006-04-01), None
patent: 58-97863 (1983-06-01), None
patent: 03-218638 (1991-09-01), None
patent: 5-206045 (1993-08-01), None
patent: 5-206053 (1993-08-01), None
patent: 6-089904 (1994-03-01), None
patent: 6-310533 (1994-11-01), None
patent: 07-142421 (1995-06-01), None
patent: 2530990 (1996-09-01), None
patent: 8-279475 (1996-10-01), None
patent: 9-17867 (1997-01-01), None
patent: 9-199719 (1997-07-01), None
patent: 10-163123 (1998-06-01), None
patent: 2000-012481 (2000-01-01), None
patent: 2003-007636 (2003-01-01), None
patent: 2003-086529 (2003-03-01), None
patent: 2003-528462 (2003-09-01), None
patent: 2004-014878 (2004-01-01), None
patent: 2004-158627 (2004-06-01), None
patent: WO 98/34268 (1998-08-01), None
patent: WO 03/014979 (2003-02-01), None
Chinese Office Action with English translation issued in corresponding Chinese Patent Application No. CN 2004800046349, mailed Mar. 30, 2007.
International Search Report corresponding to application No. PCT/JP2004/001473, dated Apr. 13, 2004.
D. Lenoble et al., “Reliable and enhanced performances of sub-0.1 μm pMOSFETs doped by low biased Plasma Doping”, 2000 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pp. 110-111, 2000.
Y. Kiyota, “Surface Reaction Doping using Gas Source for Ultra Shallow Junctions”, Japan Society of Applied Physics, 2000.
Y. Kiyota, “Role of hydrogen during rapid vapor-phase doping analyzed by x-ray photoelectron spectroscopy and Fourier-transform infrared-attenuated total reflection”, Journal of Vacuum Science and Technology A 16(1), pp. 1-5, Jan./Feb. 1998.
Y. Kiyota, “Surface Reaction Doping using Gas Source for Ultra shallow Junction”, Silicon technology No. 39, pp. 9-11, Jun. 2002.
Y. Sasaki et al., “Gas Phase Doping at Room Temperature”, Extended Abstracts of International Workshop on Junction Technology 2002, pp. 39-40.
Y. Sasaki et al., B2H6Plasma Doping with “In-situ he Pre-amorphization”, 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 180-181.
D. Lenoble et al., “Reliable and enhanced performances of sub-0.1 μm pMOSFETs doped by low biased Plasma Doping”, 2000 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pp. 110-1111, 2000.
Y. Kiyota, “Surface Reaction Doping using Gas Source for Ultra Shallow Junctions”, Japan Society of Applied Physics, 2000.
Y. Kiyota, et al., “Role of hydrogen during rapid vapor-phase doping analyzed by x-ray photoelectron spectroscopy and Fourier-transform infrared-attenuated total reflection”, Journal of Vacuum Science and Technology A 16 (1), pp. 1-5, Jan./Feb. 1998.
Y. Kiyota, “Surface Reaction Doped using Gas Source for Ultra Shallow Junction”, Silicon Technology No. 39, pp. 9-11, Jun. 2002.
Y. Sasaki et al., “Gas Phase Doping at Room Temperature”, Extended Abstracts of International Workshop on Junction Technology, pp. 39-40, 2002.
Y. Sasaki et al., B2H6Plasma Doping with “In-situ He Pre-amorphization”, 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 180-181.
Chinese Office Action issued in corresponding Chinese Patent Application No. CN 2004800046349, mailed Mar. 30, 2007.
Talwar et al., “Study of Laser Thermal Processing (LPT) to Meet Sub 130 nm Node Shallow Junction Requirements”, 2000, pp. 175-177.
Ito et al., “Flash Lamp Annealing Technology for Ultra-shallow Junction Formation”, Extended Abstract of International Workshop on Junction Technoloy, 2002, pp. 23-26.
Yamamoto et al., “Impact of Pre-Amorphization for the Reduction of Contact Resistance Using Laser Thermal Process”, Extended Abstract of International Workshop on Junction Technoloy, 2002, pp. 27-30.
Kagawa et al., Influence of Pulse Duration on KrF Excimer Laser Annealing Process for Ultra Shallow Junction Formation, Extended Abstract of International Workshop on Junction Technoloy, 2002, pp. 31-34.
Ito et al., “Improvement of Threshold Voltage Roll-off by Ultra-shallow Junction Formed by Flash Lamp Annealing”, 2003, pp. 53-54.
Yamashita, F., et al., “Direct Joule Heating of Nd-Fe-B Based Melt-Spun Powder and Zinc Binder”, 1999, IEEE.
Chu, P.K., et al., “Part one of two, Plasma Doping: Progress and potential”, Solid State Technology, Sep. 1999, pp. 55-60, www.solid-state.com.
Chu, P.K., et al., “Part two of two, Plasma Doping: Progress and potential”, Solid State Technology, Oct. 1999, pp. 77-82, www.solid-state.com.
Hori, A., et al., “CMOS Device Technology toward 50 nm Region—Performance and Drain Architecture—”, IEDM, 1999, pp. 641-644, IEEE.
Kwok, Dixon, T.K., et al., “Energy distribution and depth profile in BF3plasma doping”, Surface and Coatings Technology, 2001, pp. 146-150, vol. 136, Elsevier Science B.V.
Yamashita, F., et al., “Nd-Fe-B Thin Arc-shaped Bonded Magnets for Small DC Motors Prepared by Powder Compacting Press with Ion-implanted Punches”, J. Mgn. Soc. Japan, 2001, pp. 683-686, vol. 25, No. 4-2.
Yamashita, F., et al., “Preparation of a Solid Rotor Composed of a Highly Dense Ring-Shaped RE Bonded Magnet and an Iron-Dust Core”, Trans. Magn. Soc. Japan., 2002, pp. 111-114, vol. 2 No. 3.
Mizuni, B., “Ultra Shallow Junction for sub-50NM CMOS—The role of Plasma Doping-”, UJTLab, pp. 10-13, Ultimate Junction Technologies Inc.
Sasaki, Y., et al., “B2H6Plasma Doping with In-situ He Pre-amorphization”, Symposium on VLSI Technology Digest of Technical Papers, 2004, pp. 180-181, IEEE.
Sasaki, Y., et al., “Plasma Doped Shallow Junction Formation”, Matsushita Technical Journal,
Jin Cheng-Guo
Mizuno Bunji
Sasaki Yuichiro
McDermott Will & Emery LLP
Mulpuri Savitri
Panasonic Corporation
LandOfFree
Method for introducing impurities and apparatus for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for introducing impurities and apparatus for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for introducing impurities and apparatus for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4121830