Method for interfacing a synchronous memory to an...

Details Method for interfacing a synchronous memory to an... Method for interfacing a synchronous memory to an...

2005-09-20

2005-09-20

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C365S189011, C365S233100, C711S167000

Reexamination Certificate

active

06948084

ABSTRACT:
A method and logic for providing an asynchronous interface to a synchronous memory is disclosed. One embodiment of the present invention provides for a memory having a first logical unit which is operable to generate a synchronized clock signal in response to a chip select signal to the memory. The memory comprises synchronous memory arrays. The synchronized clock signal is input to the selected synchronous memory array. This allows an access to the synchronous memory to complete within a timing budget of the asynchronous interface. Furthermore, the memory has a second logical unit which is operable, in response to the chip select signal and a second signal input to the memory, to put an input/output bus coupled to the synchronous memory into a high impedance state by the end of the memory access. The second input signal may be a read enable or a write enable signal.

REFERENCES:
patent: 5398212 (1995-03-01), Imura et al.
patent: 5625593 (1997-04-01), Kimura
patent: 5926434 (1999-07-01), Mori
patent: 6178138 (2001-01-01), Derbenwick et al.
patent: 6532522 (2003-03-01), Barth et al.
patent: 6658544 (2003-12-01), Gray

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