Method for integrating high-voltage device and low-voltage devic

Details Method for integrating high-voltage device and low-voltage devic Method for integrating high-voltage device and low-voltage devic

1999-09-02

2000-09-26

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438275, 438297, 438298, H01L 218238

Patent

active

061241598

ABSTRACT:
A method for integrating a high-voltage device and a low-voltage device. A substrate has a high-voltage device region, a low-voltage device region and a scribe region, wherein a patterned insulating layer is formed on the substrate in the high-voltage device region and the scribe region. A grade region is formed in the substrate exposed by the patterned insulating layer in the high-voltage device region. A plurality of protuberances is formed on the substrate exposed by the patterned insulating layer in the high-voltage device region and in the scribe region. The patterned insulating layer and the protuberances are removed to form recesses at locations of the protuberances. A first gate structure and a second gate structure are respectively formed on the substrate between the grade region in the high-voltage device region and on the substrate in the low-voltage device region while using the recesses as alignment marks. A lightly doped region is formed in the substrate exposed by the second gate structure in the low-voltage device region. Spacers are formed on sidewalls of the first gate structure and the second gate structure. A heavily doped region and a source/drain region are respectively formed in the substrate exposed by the spacer in the high-voltage device region and the low-voltage device region, wherein the heavily doped region and the grade region together form a double diffused drain region.

REFERENCES:
patent: 4590663 (1986-05-01), Haken
patent: 5024960 (1991-06-01), Haken
patent: 5254487 (1993-10-01), Tamagawa
patent: 5834352 (1998-11-01), Choi

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