Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-06
2002-06-25
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S202000, C438S204000, C438S207000, C438S234000, C438S237000, C438S048000
Reexamination Certificate
active
06410377
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for integrating processes in integrated circuits, and, more particularly, relates to a method for integrating a fabrication of a CMOS sensor and a high voltage device.
2. Description of the Prior Art
A photo diode based on the theorem of a P-N junction can convert light into an electrical signal. Before energy in the form of photons strikes the photo diode, there is an electric field in the P-N junction. The electrons in the N region do not diffuse forward to the P region and the holes in the P region do not diffuse forward to the N region. When enough light strikes the photo diode, the light creates a number of electron-hole pairs. The electrons and the holes diffuse forward to the P-N junction. While the electrons and the holes reach the P-N junction as a result of the effect of the inner electric field across the junction, the electrons flow to the N region and the holes flow to the P region. Thus, a current is induced between the P-N junction electrodes. Ideally, a photo diode in the dark is open-circuit. In other words there is no current induced by light while the photo diode is in the dark.
High voltage devices are currently being used in many applications. For example, high voltage devices are required to program or erase a non-volatile memory cell. A lateral diffusion MOS (LDMOS) transistor has a lower “on” resistance, a faster switching speed, and a lower gate drive power dissipation.
On the development of Ultra Large Scale Integrated (ULSI), the application of a product is going to depend on a multi-chip of an integrated function. Accompanying this trend, it is valuable to integrate different kinds of applied devices, such as CMO sensors, high voltage device and low voltage device, etc. Consequentially, it is necessary to find a method of integrating a CMOS sensor and a high voltage device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for integrating a fabrication of a CMOS sensor and a high voltage device.
Another object of the invention is using the P conductive type field and the P conductive type well as isolations to increase the effect of isolation and forming high voltage devices between these isolations.
In order to achieve the stated objects of the invention, the method of the present invention comprises the following steps: First, a substrate of a first conductive type is provided with a first region and a second region. Then, a first well of a second conductive type is formed in the substrate of the second region, the second conductive type being opposite to the first conductive type. Next, a plurality of filed oxide regions are formed on the substrate to define a first active region of the sensor in the first region and a second active region of the high voltage device in the second region. The first well is in a lateral position with respect to the substrate of the second active region and one of the field oxide regions is floating on the first well. Next, a first doped region of the second conductive type of formed in the substrate of the first active region of the sensor and in the substrate of the second region of the first well. The first doped region in the second region caps the field oxide region in the first well. Thereafter, a second well of the first conductive type is formed in the substrate, wherein the second well in the first region is under each one of the field oxide regions and the second well in the second region is adjacent to the first well in the second active region. Then, a gate oxide layer is formed on the substrate except on the field oxide regions. Next, a polysilicon gate electrode is formed covering a portion of the second well and a portion of the first well in the second active region, wherein the polysilicon gate electrode is also covering a portion of the field oxide region on the first well. Last, a source region and a drain region are formed in the substrate of the second active region. The source region is in the substrate of the second well around the polysilicon gate electrode. The drain region is in the substrate of the first well around a lateral of the field oxide region which is not covered by the polysilicon gate electrode.
REFERENCES:
patent: 6096589 (2000-08-01), Lee et al.
patent: 6169318 (2001-01-01), McGrath
patent: 6303419 (2001-10-01), Chang et al.
patent: 6306700 (2001-10-01), Yang
Hwang Ching-Chun
Yang Sheng-Hsiung
Lebentritt Michael S.
Pyonin Adam
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