Method for integrated circuit planarization

Details Method for integrated circuit planarization Method for integrated circuit planarization

2000-04-14

2002-06-18

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

C438S762000, C438S763000, C100S211000

Reexamination Certificate

active

06407006

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices, including integrated circuit (“IC”) devices. More particularly, it relates to a methods and apparatus for planarizing and/or embossing patterns onto surfaces of semiconductor devices that contain silica dielectric coatings, and particularly nanoporous silica dielectric coatings, as well as to semiconductor devices produced by these methods and apparatus.
BACKGROUND OF THE INVENTION
Processes used for the fabrication of semiconductor devices almost invariably produce surfaces which significantly deviate from a planar configuration. With the trend toward greater large scale integration, this problem is expected to increase. For instance, the production of integrated circuits typically requires multiple layers to be formed sequentially on a semiconductor substrate. Many of these layers are patterned by selective deposition or selective removal of particular regions of each such layer. It is well known that small deviations from the planar, condition in underlying layers become more pronounced with the addition of multiple additional layers of semiconductor and circuit features. Non-planar substrate surfaces can cause many problems that adversely impact the yield of finished products. For example, variations in interlevel dielectric thickness can result in failure to open vias, poor adhesion to underlying materials, step coverage, undesirable bends or turns in conductive metal layers, as well as “depth-of-focus” problems for optical lithography.
In order to effectively fabricate multiple layers of interconnects it has become necessary to globally planarize the surface of certain layers during the multi-step process. Planarizing smoothes or levels the topography of microelectronic device layers in order to properly pattern the increasingly complex integrated circuits. IC features produced using optical or other lithographic techniques require regional and global dielectric planarization where the lithographic depth of focus is extremely limited, i.e., at 0.35 &mgr;m and below. As used herein, the term “local planarization” refers to a condition wherein the film is planar or flat over a distance of 0 to about 5 linear micrometers. “Regional planarization” refers to a condition wherein the film is planar or flat over a distance of about 5 to about 50 linear micrometers. “Global planarization” refers to a condition wherein the film is planar or flat over a distance of about 50 to about 1000 linear micrometers. Without sufficient regional and global planarization, the lack of depth of focus will manifest itself as a limited lithographic processing window.
One previously employed method of planarization is the etch-back technique. In that process, a material, i.e., a planarizing material, is deposited on a surface in a manner adapted to form a surface relatively free of topography. If the device layer and the overlying material layer have approximately the same etch rate, etching proceeds through the planarizing material and into the device layer with the surface configuration of the planarizing layer being transferred to the device material surface. Although this technique has been adequate for some applications where a modest degree of planarity is required, present planarizng materials and present methods for depositing the planarizing material are often inadequate to furnish the necessary planar surface for demanding applications such as in submicron device fabrication.
The degree of planarization is defined as the difference between the depth of the topography on the device surface h
t
, and the vertical distance between a high point and a low point on the overlying material surface h
d
, divided by the depth of the topography on the device surface h
t
:
h
t
-
h
d
h
t
The degree of planarization, in percent, is
h
t
-
h
d
h
t
×
100
Generally, for typical device configurations, planarization using the etch-back technique has not been better than approximately 55% as calculated by the method described above for features greater than 300 microns in width. The low degree planarization achieved by this technique is attributed to a lack of planarity in the planarizing material. Thus, for elongated gap-type features greater than 300 microns in width and 0.5 microns in depth, the usefulness of an etch-back technique has been limited.
U.S. Pat. No. 5,736,424, incorporated herein by reference in its entirety, describes a method for planarizing surfaces of substrates, such as semiconductor materials, by adding a pressing step to an etch-back process. In this reference, an optically flat surface is impressed on a curable viscous polymer coating on the substrate surface in need of planarization, followed by polymerization of the coating. The polymer is selected to etch at the same rate as the surface in need of planarization, and the polymer coating is etched down to the substrate, which is planarized by the process. While an improved planarization is claimed, apparently by starting the etch-back with a flatter surface, an added process step and complexity is required. In addition, this reference fails to provide a solution for planarizing substrates coated with nanoporous dielectric films, since by their nature, such low density films cannot be etched at the same rate as the underlying substrate.
Chemical mechanical polishing (CMP) is another known method that has been effectively used in the art to globally planarize the entire surface of dielectric layers. According to this method, a grainy chemical composition or slurry is applied to a polishing pad and is used to polish a surface until a desired degree of planarity is achieved. CMP can rapidly remove elevated topographical features without significantly thinning flat areas. However, CMP does require a high degree of process control to obtain the desired results.
Dielectric films formed of organic polymers, such as polyarylene ether and/or fluorinated polyarylene ether polymers, have been planarized by applying CMP to a partially cured film, followed by a final curing, as described in co-owned U.S. Ser. No. 09/023,415, filed on Feb. 13, 1998, the disclosure of which is incorporated by reference herein in its entirety. However, this reference fails to disclose how to planarize a silicon-based nanoporous dielectric material on the surface of a substrate.
Further, these previous methods are inadequate for providing localized planarization on different areas of a substrate surface, or for embossing other types of topography onto specific portions of a substrate surface. This is particularly important as the move towards ever larger integrated surface devices requires multiple planar surfaces, vias, trenches and the like, on disparate portions of a single substrate.
In addition, as IC feature sizes approach 0.25 &mgr;m and below, problems with interconnect RC delay, power consumption and signal cross-talk have become increasingly difficult to resolve. The integration of low dielectric constant materials for interlevel dielectric (ILD) and intermetal dielectric (IMD) applications, is helping to solve these problems. One type of such low dielectric constant materials are nanoporous films prepared from silica, i.e., silicon-based materials. When air, with a dielectric constant of 1, is introduced into a suitable silica material having a nanometer-scale pore structure, dielectric films with relatively low dielectric constants (“k”), e.g., 3.8 or less, can be prepared on substrates, such as silicon wafers, suitable for fabricating integrated circuits.
There is also a need in the art to pattern the surfaces of potential microelectronic device s or integrated circuits. A number of such methods are known, and include photolithography, electron-beam lithography, and x-ray lithography. With electron-beam lithography, the beam is rastered across the surface of the article to produce the pattern. This is a slow, expensive process. Other previous methods for patterning include a method and apparatus for micro-contact printing that requires complex control mechanisms to kee

Affiliated with

Also associated with

Rating

Method for integrated circuit planarization does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for integrated circuit planarization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for integrated circuit planarization will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2892832