Method for initiating internal parity operations in a CAM...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C714S722000

Reexamination Certificate

active

06971053

ABSTRACT:
A circuit and a method of operating the circuit is provided. The method generally comprises the steps of (A) receiving an explicit error checking instruction generated outside the circuit, (B) performing an error checking operation for at least one of a plurality of memory locations within the circuit, and (C) generating a result signal from the error checking operation.

REFERENCES:
patent: 4882731 (1989-11-01), van Gils
patent: 5086429 (1992-02-01), Gray et al.
patent: 5392301 (1995-02-01), Fukushima
patent: 5914907 (1999-06-01), Kobayashi et al.
patent: 5978947 (1999-11-01), Kim et al.
patent: 6681359 (2004-01-01), Au et al.
patent: 6690595 (2004-02-01), Srinivasan et al.
patent: 6691252 (2004-02-01), Hughes et al.
patent: 6728124 (2004-04-01), Ichiriu et al.

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