Method for increasing tolerance of contact extension...

Details Method for increasing tolerance of contact extension... Method for increasing tolerance of contact extension...

2000-09-26

2002-12-17

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S250000, C438S254000, C438S396000, C438S393000, C438S397000

Reexamination Certificate

active

06495417

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for increasing tolerance of contact extension alignment in a dynamic random access memory (DRAM), and more particularly to a method for increasing tolerance of contact extension alignment in a capacitor over a bit line (COB) of a dynamic random access memory.
2. Description of the Related Art
Dynamic random access memory is applied broadly in the field of integrated circuits devices, and more importantly, in the electronics industry. Dynamic random access memories with higher capacitance are necessary for the development of the industry. As a result, dynamic random access memories with higher density and capacitance are of great interest and are developed by the related industry. How to keep the quality as the size of the device is reduced is now a task for the industry to overcome.
For the storage of digital data, the capacitance of the memory is called a “bit” and the unit for data storage in a memory is called a “memory cell”. The memory cell is arranged in array, consisting of columns and rows. A set of a column and a row represents a specific address. Memory cells in the same column or the same row are coupled by a common wiring line, which is called a word line. The vertical wiring line, which is used to data transmitting is called a bit line. The current design of DRAM is composed of a transistor, which is series-coupled to a capacitor to replace the original memory consisting of three transistors. In this manner, the circuit is simplified and the density of the device can be increased.
For the design of Ultra Large Scale Integration (ULSI) dynamic random access memory, the lithography and alignment controlling the contact is more and more critical as the device size reduces gradually. Misalignment can severely impact the functionality of a device. It may cause circuit failures of a dynamic random access memory. To insure that contacts between interconnect layers are made properly even if a slight misalignment occurs during masking steps, extra space is usually included in a design around contacts and other conductive features. However, the problem of Misalignment beyond certain minimum tolerance due to shrinking of the design rule still cannot be resolved completely.
FIG. 1
is a schematic cross sectional diagram of a conventional capacitor over a bit line of a dynamic random access memory. Firstly, a substrate
100
having a field oxide region
102
, source/drain regions
106
a
,
106
b
is provided. Then, a polysilicon layer used as a gate electrode
104
a
and a word line
104
b
is formed. Next, an oxide layer
112
is formed to cover the gate electrode
104
a
and the word line
104
b
. polysilicon layer is formed then defined as bit lines
114
a
and
114
b
. Moreover, two planarized insulating layers
116
a
,
116
b
are provided on the bit lines
114
a
,
114
b
and a contact hole is formed by patterning to etch the planarized insulating layers
116
a
,
116
b
and the oxide layer
112
to expose a portion of the source/drain regions
106
a
,
106
b
. The contact hole is filled with a polysilicon layer
118
to serve as a first electrode of the capacitor. The first electrode of the capacitor is formed by patterning to etch the polysilicon layer
118
wherein the pattern, which defines the first elect rode of the capacitor, is formed with a result of misalignment. The misalignment may be formed due to errors of the lithography process. Because of the misalignment, a trench
122
is formed after the sequential etching process. A dielectric layer
120
is deposited on the polysilicon layer
118
, the planarized insulating layer
116
b
and the trench
122
. The trench
122
is covered with poor step coverage. Finally, a polysilicon layer
124
is formed on the dielectric layer
120
to serve as a second electrode of the capacitor.
As shown in
FIG. 1
, the device may not be reliable, because the trench
122
may cause the failure of the circuit when the device size reduces and the isolation between the gate electrode
104
a
, the bit line
114
a
and the first electrode of the capacitor
118
degrades. The trench
112
may also cause a failure of the capacitor due to the poor step coverage of the dielectric layer
120
in the trench
122
.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to increase tolerance of contact extension alignment in a capacitor over a bit line of a dynamic random access memory that substantially prevents the failure of the electrode of the capacitor from being formed. Furthermore, circuit failures of a capacitor over a bit line of a dynamic random access memory due to misalignment can be avoided.
It is another object of this invention that the alignment limitation of the contact extension can be reduced in spite of the shrinking of the design rule.
It is a further object of this invention that the difficulty of the etching process can be reduced as the device size decreases in order to obey the design rule.
To achieve these objects, and in accordance with the purpose of the invention, a method for increasing tolerance of contact extension alignment in a capacitor over a bit line of a dynamic random access memory is disclosed. Firstly, a substrate having a gate, a bit line and a source/drain region is provided and an insulating layer is formed on the substrate. Then, a dielectric layer is deposited on the insulating layer. Moreover, a contact hole is formed by defining and etching the dielectric layer and the insulating layer to expose a portion of the source/drain region. Furthermore, a conductive layer is deposited on the dielectric layer and the contact hole, wherein the etching selectivity ratio of the conductive layer is near the etching selectivity ratio of the dielectric layer. Finally, an electrode of the capacitor is formed by defining and etching the conductive layer, whereby the dielectric layer protects the portion of the electrode that is beneath the dielectric layer from being etched when misalignment occurs.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 4714686 (1987-12-01), Sander et al.
patent: 5338750 (1994-08-01), Tuan et al.
patent: 6143602 (2000-11-01), Jang
patent: 6277688 (2001-08-01), Tseng
patent: 6325676 (2001-12-01), Jung et al.
patent: 6358827 (2002-03-01), Chen et al.
Wolf et al. Silicon Processing for the VLSI Era, vol. 1, Process Technology 1986, Lattice Press, pp. 177, 191-192, 529-532.

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