Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-18
2004-03-02
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S246000, C438S387000, C438S389000, C438S244000
Reexamination Certificate
active
06699747
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method for increasing a capacitance in a storage trench and to a trench capacitor having an increased capacitance.
The invention can be used in memory circuits, such as, for example, dynamic random access memories (DRAM) and other semiconductor circuits.
In trench DRAM modules, a storage of charge is based in a capacitor as a storage element, which is formed in a pot-shaped manner. This entails not only a reduction of the cell area but also, at the same time, a reduction of the probability of alpha particles striking the cell. Such a pot-shaped capacitor is formed in a trench and is also referred to as a trench capacitor. The store of the trench cell has a trench that must keep a specific quantity of charge stored for a specific period of time.
In order to maintain and increase international competitiveness, it is necessary to continually reduce the costs that have to be expended to realize a specific electronic function, in order to increase productivity. The guarantee for increasing productivity in recent years has been and still is CMOS technology or DRAM technology. Trench DRAM technology owes its outstanding position principally to the small space requirement of the trench capacitors themselves and also to the possibility of disposing the trench capacitors in an integrated circuit with an extremely high packing density.
The continually progressing miniaturization of the structures is accompanied by a decrease in the diameter of the trench and hence its surface area, with the result that less charge can be stored in the case of conventional technology.
The prior art disclosed in U.S. Pat. No. 5,876,788 teaches a method for fabricating a dielectric for the DRAM cells. In this case, Si
3
N
4
is used, on account of its relatively high dielectric constant, as a dielectric for increasing the storage capacitance. The use of this dielectric causes a number of problems principally in the case of decreasing lateral dimensions. In order to avoid the loss of charge associated with a decreasing diameter in DRAM cells, it has been proposed to etch the trench more deeply or to reduce the thickness of the silicon nitride layer. However, etching a deeper trench would disadvantageously increase the process time and the costs for fabrication. Reducing the layer thickness of the silicon nitride film can bring about an increase in the loss due to the tunnel effect.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for increasing the capacitance in a storage trench and a trench capacitor having an increased capacitance which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which, despite an increased packing density, sufficient charge can be stored so that the functionality of a memory cell continues to be ensured.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for increasing a capacitance in a storage trench. The method includes the steps of depositing a layer of silicon oxide in the storage trench; depositing a layer of silicon over the layer of silicon oxide by a deposition method suitable for sufficient coverage of walls of the storage trench; depositing a layer having an oxidizable metal over the layer of silicon; and oxidizing the layer of silicon and the layer having the oxidizable metal to form a layer having a metal oxide and an silicon oxide.
In the method for increasing the capacitance in the storage trench, the first layer of silicon oxide is deposited in the storage trench. The layer of silicon is deposited over the first layer of silicon oxide by a deposition method which yields a sufficient coverage of the side walls of the storage trench. The layer having an oxidizable metal is deposited over the layer of silicon. The layer of silicon and the layer of oxidizable metal are oxidized to form a layer having metal oxide and silicon oxide.
In the trench capacitor having the increased capacitance, the inner wall of the storage trench is covered with the first layer of silicon oxide. The first layer of silicon oxide is covered with the layer having a metal oxide. The layer having the metal oxide is covered with a second layer of silicon oxide. The remainder of the storage trench is filled with silicon.
Chemical vapor deposition or atomic layer deposition may advantageously be used as the deposition method.
In the method according to the invention, it is advantageous if the second layer of silicon oxide is deposited over the layer having metal oxide and silicon oxide.
It is also advantageous if the layer of oxidizable metal has Ti, TIN, W, WN, Ta, TaN, WSi, TiSi or TaSi.
The oxidation is advantageously carried out in an oxygen-containing atmosphere. This achieves intensified oxidation of the respective metal.
Furthermore, it is advantageous to fill the storage trench with silicon.
For the method according to the invention, it is advantageous if the storage trench has a width of less than 140 nm.
In the method according to the invention, it is particularly preferred if the first layer of silicon oxide has a thickness of approximately 0.3 nm.
In the method according to the invention, it is likewise particularly preferred if the second layer of silicon oxide has a thickness of approximately 0.3 nm.
Furthermore, it is preferred if the first and the second layer of silicon oxide are deposited by a chemical vapor deposition process.
In the method according to the invention, it is particularly preferred if the layer of silicon has a thickness of approximately 0.5 nm.
In the method according to the invention, it is particularly preferred if the silicon used is particularly suitable for coverage of the side wall.
It is advantageous for the method according to the invention that the layer of oxidizable metal has a thickness of approximately 10 nm.
Furthermore, it is advantageous for the method according to the invention if the layer having the oxidizable metal is deposited by a chemical vapor deposition process.
With the foregoing and other objects in view there is further provided, in accordance with the invention, a trench capacitor having an increased capacitance. The trench capacitor contains a substrate having a storage trench formed therein and the storage trench is defined by side walls and a bottom. A first layer of silicon oxide covers the side walls and the bottom of the storage trench. A layer having a metal oxide covers the first layer of silicon oxide. A second layer of silicon oxide covers the layer having the metal oxide and silicon fills in a remainder of the storage trench.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for increasing the capacitance in a storage trench and a trench capacitor having an increased capacitance, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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Karcher Wolfram
Kegel Wilhelm
Ruff Alexander
Schrems Martin
Fourson George
Garcia Joannie Adelle
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
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