Method for increasing latch-up immunity in CMOS devices

Details Method for increasing latch-up immunity in CMOS devices Method for increasing latch-up immunity in CMOS devices

1997-03-17

1998-06-23

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438221, 438222, 438223, 438433, 438524, 148DIG40, 148DIG50, 148DIG85, 148DIG86, 257371, 257374, 257520, H01L 21336

Patent

active

057705046

ABSTRACT:
The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by reducing the mobility of carriers between the devices. The preferred embodiment uses an implant formed beneath trench isolation between n-channel and p-channel devices. This implant preferably comprises relatively large/heavy elements implanted into the wafer beneath the trench isolation. The implant elements reduce the mobility of the charge carriers. This increases the latch-up holding voltage and thus reduces the likelihood of latch-up. The implants can be formed without the need for additional photolithography masks.

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