Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1999-03-23
2000-06-27
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438672, 438675, 438647, 438637, H01L 2144, H01L 214763
Patent
active
060806664
ABSTRACT:
A method for increasing landing pad area is disclosed. Firstly, providing a fundamental structure, wherein shallow trench isolation (STI) is used and acting as an electrical isolation inside of substrate. Moreover, there are at least two gates with an isolation layer on top of the substrate and covered with a dielectric layer. Between the neighboring gates there is a contact hole that penetrates the dielectric layer from the top of the dielectric layer to the substrate. Taking this fundamental structure as the starting point for forming a conductor within the contact hole. Etching back the dielectric layer and exposing its top surface and a portion of sidewalls. Finally, a protection layer on top of the exposed portion of sidewalls of the conductor is formed in order to expand the landing pad area. After all, one would still be able to increase the landing pad area even though the distance between two gates is rather small. This method can solve all the puzzles caused by alignment accuray shift during post-process.
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patent: 5854127 (1998-12-01), Pan
patent: 5909636 (1999-06-01), Nguyen et al.
patent: 5914518 (1999-06-01), Nguyen et al.
Lee Hal
Wu Der-Yuan
Bowers Charles
Lee Hsien-Ming
United Microelectronics Corp.
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