Method for increasing isolation ability using shallow trench

Details Method for increasing isolation ability using shallow trench Method for increasing isolation ability using shallow trench

1999-03-29

2001-02-13

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S276000, C438S524000, C438S527000, C438S296000, C438S424000

Reexamination Certificate

active

06187637

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates the method for increasing isolation ability, more particularly by forming the shallow trench neighbouring between BN
+
ROM cell.
2. Description of the Prior Art
Basically the new fashion way, to semiconductor device will be gradually fabricated smaller than before. Especially for the new generation, the manufactured technology for ROM of semiconductor device will be advantageously the coming twenty-first century. The ideal memory would be low cost, high performance, high density, with low power dissipation, random access, non-volatile, easy to test, highly reliable, and standardized throughout the industry. Also, the better cell isolation is expected for increasing the strength of device anti-punch through. Unfortunately those memory technologies which did not offer these advantages to some extent were one by one successfully challenged by the ROM memories. Therefore, how to improve the better cell isolation performance could not wait too long.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming a shallow trench that substantially can increase isolation ability. In one embodiment, a shallow trench into semiconductor device is formed on a wafer. Therefore the wafer owns a semiconductor substrate and wherein a first gate oxide layer is formed on the semiconductor substrate. A nitride layer is formed on the gate oxide layer. Then the method will include the following statement. Firstly a deep well layer is formed into the semiconductor substrate. Then patterning oxide layer and the nitride layer is carried out. Thereafter trenches is formed. The portion of silicon nitride layer and gate oxide layer will be etched according to the pattern of the gate oxide layer and the nitride layer. Sequentially first implanting a couple of device cell into the deep well of semiconductor substrate is achieved. Then the couple of device cell is annealed. The whole silicon nitride layer is removed. Not only the second implanting cell device will be obtained but also the third implanting cell device will be achieved. The first gate oxide layer is removed. A second gate oxide, a polysilicon layer and a tungsten silicide layer are in sequence deposited. Then the polysilicon gate is defined. The polysilicon gate is etched that abuts between the couple of cell device. Cell isolation implanted behind the trench wherein the isolation is formed thus excited between said couple of cell device. The cell device and cell isolation both are annealed. Consequentially a silicon oxide is conformably deposited in order to fulfill the trench. Finally the surface of silicon oxide is planarized.


REFERENCES:
patent: 5504030 (1996-04-01), Chung et al.
patent: 5536670 (1996-07-01), Hsue

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