Method for increasing capacitance

Details Method for increasing capacitance Method for increasing capacitance

1998-06-12

2001-05-29

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S252000, C438S238000, C438S239000

Reexamination Certificate

active

06238972

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the formation of high capacitance structures in integrated circuit devices and, more particularly, to the formation of electrodes which incorporate at least one textured surface.
2. Description of the Related Art
Historically, increasing the density of integrated circuit devices has been accomplished in part by decreasing the size of structures such as wiring lines and transistor gates and by decreasing the separation between the structures which make up the integrated circuit device. Reducing the size of circuit structures is generally referred to as decreasing the “design rules” used for the manufacture of the integrated circuit device. For dynamic random access memories (DRAMs), information is typically stored by selectively charging or discharging each capacitor of an array of capacitors formed on the surface of a semiconductor substrate. Most often, a single bit of binary information is stored at each capacitor by associating a discharged capacitor state with a logical zero and a charged capacitor state with a logical one. The surface area of the plates of the memory capacitors determines the amount of charge that can be stored on each of the capacitors, given the typical fixed operating voltage of a memory, the electrode separation that can reliably be manufactured, and the dielectric constant of the capacitor dielectric typically used in the capacitors. Reducing the surface area occupied by such a DRAM capacitor in accordance with reduced design rules tends to reduce the surface area of the capacitor plates and reduce the amount of charge that can be stored on the memory capacitor (i.e., the capacitance).
The amount of charge stored on memory capacitors typically must be large enough to obtain reliable operation of the memory. For recent ultra large scale integration (“ULSI”) DRAM designs, further reductions in the amount of charge stored on the DRAM memory capacitors could prevent the information stored on the capacitor from reliably being read out. In addition, because charge inevitably drains from memory capacitors, DRAMs require a periodic refresh of the charge stored on each of the capacitors of the DRAM to ensure that the stored charge remains above the minimum detectable level. Further reductions in capacitance would require more frequent refresh operations for the DRAM, which are undesirable because at least portions of the DRAM are unavailable for the reading and writing of information during refresh operations.
To address the challenges of reduced structure sizes, DRAM designs have been proposed which incorporate capacitors having vertical extensions above the surface of the substrate (i.e., “stacked” capacitors) or below the surface of the substrate (i.e., “trench” capacitors). By adopting a more three-dimensional structure, such DRAM designs provide memory capacitors having larger capacitances but which consume less of the substrate surface area. Although stacked capacitor and trench capacitor designs involve more complicated structures which are more difficult to manufacture, these designs have recently been adopted with at least some success. Alternative, less expensive and more easily manufactured structures providing improved capacitance are desirable. In addition, it is desirable to reduce the vertical extent of the storage capacitor to allow the production of more planar device structures. There additionally remains a need to increase the capacitance of DRAM storage capacitors while decreasing the amount of surface area consumed by the DRAM storage capacitor on the surface of the semiconductor substrate.
One technique that has been proposed for increasing the capacitance obtained for a fixed substrate surface area is to use rugged or textured silicon as the bottom plate for the memory capacitor. The advantages of this technique are illustrated in part in
FIG. 1
, which shows in cross-section a portion of a DRAM having a memory capacitor with a lower plate electrode formed from textured silicon. The illustrated DRAM consists of a silicon substrate
10
, field oxidation regions
12
, source/drain regions
14
,
16
and gate electrode
18
of the memory cell's transfer field effect transistor (“FET”) and a wiring line
20
formed over one of the field oxide regions
12
. The wiring line
20
interconnects portions of the DRAM in the well-known manner and the transfer FET acts as a switch during capacitor read out and write operations. In such a DRAM, the memory capacitor may be connected to a source/drain region
16
of the transfer FET by a vertically extending interconnect
22
which terminates in a plate
24
formed from conventional polysilicon. A layer of textured silicon
26
is formed on the upper surface of the conventional polysilicon plate
24
to complete the lower electrode of the charge storage capacitor. A thin dielectric layer
28
covers the surface of both the layer of textured silicon
26
and the exposed portions of the plate
24
, and a layer of doped polysilicon
30
is formed on the dielectric layer
28
to serve as the upper electrode for the capacitor. By using textured silicon within the lower electrode of the capacitor, the surface area of the capacitor is increased without extending the capacitor electrodes laterally, so that the illustrated structure has improved capacitance for a fixed surface area.
A variety of techniques have been used to produce textured silicon for use in semiconductor devices like the DRAM illustrated in FIG.
1
. Watanabe, et al., “Device Application and Structure Observation for Hemispherical-Grained Si,” describes the formation of hemispherical-grained polycrystalline silicon (“HSG-Si”, used hereinafter to refer to textured silicon) by low pressure chemical vapor deposition (LPCVD) from silane gas (SiH
4
). The surface roughness or texture of the HSG-Si films was maximized so that the HSG-Si films could be used as plates of DRAM memory capacitors, with maximum capacitances being obtained for polysilicon (HSG-Si) deposited at a substrate temperature of 590° C. Substrate deposition temperatures of ten degrees higher or lower than 590° C. produced an unacceptable surface texture, that is, these conditions produced an undesirably flat surface which did not provide appreciably larger capacitance electrodes than conventional polysilicon. Capacitors made using a lower electrode of HSG-Si deposited using LPCVD onto a substrate at a temperature of 590° C. exhibited a capacitance per unit area approximately two times larger than similar capacitors made using flat lower electrodes deposited at substrate temperatures of either 580° C. or 600° C. (or higher).
Fazan, et al., “Electrical Characterization of Textured Interpoly Capacitors for Advanced Stacked DRAMs,” describes an alternative process for forming a textured surface on a layer of doped polycrystalline silicon. Wet oxidation at 907° C. is used to grow an oxide film on the surface of a doped polysilicon layer and then the oxide film is etched to produce a textured surface on the polycrystalline silicon. Etching of the oxide layer grown on the polysilicon layer results in creation of a textured polysilicon surface due to the greater levels of oxidation that occurs along the grain boundaries of doped polysilicon layers coupled with the subsequent removal of the oxide from the polysilicon grain boundaries. The extent of surface roughness produced in this process directly relates to the size of the polysilicon grains, so that small grained films are required to produce desirable levels of surface texture.
The article by Sakao, et al., “A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64 Mb DRAMs,” 1990
IEDM
describes the formation of a DRAM capacitor incorporating HSG-Si to provide increased storage capacitance. Formation of the Sakao capacitor proceeds as follows. After the formation of the source, drain and gate of the transfer FET, a layer of oxide is formed over the gate and word line. A contact via is opened to the drain of the tr

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