Method for improving yield of a layout and recording medium...

Details Method for improving yield of a layout and recording medium... Method for improving yield of a layout and recording medium...

2007-07-11

2010-10-19

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07818697

ABSTRACT:
A yield of a semiconductor layout may be improved by selecting a pattern that does not satisfy at least one of multiple rules within the layout, adding a margin to a predetermined value of the at least one of the rules associated with selected pattern, based on a ground rule and a recommended rule of each of the rules, calculating an overall fail rate of at least one of the rules that varies according to the addition of the margin, and determining an adjusted margin to be added based on the calculated overall fail rate.

REFERENCES:
patent: 6507930 (2003-01-01), Bass et al.
patent: 6901564 (2005-05-01), Stine et al.
patent: 7076749 (2006-07-01), Kemerer et al.
patent: 2001/0049811 (2001-12-01), Taoka
patent: 2001-350250 (2001-12-01), None
patent: 2004-127067 (2004-04-01), None

Affiliated with

Also associated with

Rating

Method for improving yield of a layout and recording medium... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for improving yield of a layout and recording medium..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for improving yield of a layout and recording medium... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4234877