Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1999-08-27
2002-05-28
Lee, Thomas (Department: 2182)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C703S019000, C703S023000, C716S030000, C716S030000
Reexamination Certificate
active
06397341
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to behavioral synthesis, and more particularly to behavioral synthesis linked to logic synthesis.
BACKGROUND OF THE INVENTION
The following co-pending U.S. patent application, which is herein incorporated by reference, represents background to the present invention: “Behavioral Synthesis Links To Logic Synthesis,” filed on May 12, 1995, with inventors Ronald A. Miller, Donald B. MacMillen, Tai A. Ly and David W. Knapp, having McDermott, Will & Emery docket number of 49725-021 and U.S. Pat. Ser. No. 08/440,101. This co-pending application will hereinafter be referred to as the Miller application.
Behavioral synthesis allows the designer of complex digital integrated circuits to specify the design at a relatively high-level of abstraction, which provides a variety of advantages in the design process. In particular, behavioral synthesis allows the design to be specified in a high-level hardware description language (HLHDL) that is more oriented towards expressing the desired behavior than the underlying hardware mechanisms by which such behavior will be accomplished. Some of the advantages of such behavioral HLHDL specifications are as follows. Since behavioral descriptions are closer to the overall behavior desired, they tend to be more intuitive and easier for the circuit designer to write. Behavioral descriptions tend to be shorter than more hardware-oriented descriptions and therefore tend to be quicker to write. Because behavioral descriptions are at a high-level of abstraction, they tend to simulate much faster than lower-level descriptions. All of these above advantages enhance the ability of the circuit designer to explore architectural alternatives and a variety of design trade-offs.
The basic process by which behavioral synthesis is accomplished, according to the Miller application, is shown in FIG.
1
. The process of
FIG. 1
is accomplished by the “Behavioral Compiler” product of Synopsys, Inc., 700 East Middlefield Road, Mountain View, Calif. The input representation is an HLHDL such as IEEE Standard 1076-1993 VHDL or IEEE Standard 1364-1995 Verilog HDL, both of which are herein incorporated by reference. Step
1510
translates the HLHDL into a “register transfer level” (RTL) description that includes high-level (i.e., multi-bit): functional units (with no delay or area information) and multiplexors. In contrast to the translation process as applied to conventional RTL synthesis, the current translation process does not infer any sequential elements. As a result, this netlist representation produced by the translation process only models data flow. Operations performed by functional units include: arithmetic operations, logical operations or conditional (i.e. comparison) operations. Note that the Miller application often uses the term “operation” to refer to what is herein called a functional unit. The logic synthesis link to behavioral synthesis is accomplished by Steps
1520
and
1530
. Step
1520
performs a quick and approximate form of logic synthesis (i.e., technology mapping), in the midst of behavioral synthesis, to provide lower-level (typically gate-level or bit-level) circuit structure for the functional units that can then be timed by Step
1530
. This lower-level representation is maintained in correspondence with the RTL description. Step
1530
performs pretiming of the circuit design produced by Step
1520
, where timing information is added to the high-level functional units for use in subsequent behavioral synthesis operations. The subsequent behavioral synthesis operations are performed by Step
1540
. The behavioral synthesis operations that can be performed include scheduling, resource sharing, allocation and post annotation. Once behavioral synthesis has been completed, and the circuit design has been fully optimized at a functional unit level, Step
1550
is executed such that a fully optimizing (and slow relative to Step
1520
) form of logic synthesis can be done to result in an optimized gate-level description of the circuit design.
The scheduling operation of Step
1540
determines in which clock cycle each functional unit executes. The resource sharing operation of Step
1540
determines which functional units have hardware implementations that can be shared, for such reasons as their operating at mutually exclusive times. The allocation operation of Step
1540
maps the functional units into a specific hardware architecture, such as a “datapath” comprising: memories, registers, arithmetic units, logical units and routing units. Functional units which require more than one clock cycle to execute are also annotated, by Step
1540
, as requiring multiple cycles. This annotation prevents the logic optimizer
1550
from attempting to fit such functional units into a single cycle.
Scheduling is a crucial behavioral synthesis activity since its assignment of functional units to clocks cycles determines such key characteristics of the overall design implementation as: clock period, latency and throughput. The delay information, aquired by Step
1530
, is essential to the scheduling process.
FIG. 2
depicts the basic procedure by which pretiming of a design, as called for by Step
1530
of
FIG. 1
, is accomplished in the Miller application. This procedure produces, for each functional unit, a “chaining table.” The chaining table provides the scheduling process of Step
1540
with delay information in a convenient form which allows the scheduler to readily ascertain the maximum number of functional units that can be fit into a clock cycle. Step
210
loops through each functional unit. For each functional unit iterated over, which shall be called the current functional unit, the following is performed. Step
220
sets all inputs of the current functional unit to time zero. All primary inputs of the circuit are set to minus infinity by Step
230
. Note that inputs to the current functional unit which have been set to zero remain at zero regardless of whether it is fed by a primary input. Further note that between Steps
280
and
290
the inputs of the current functional unit must be released from their zero setting before the next current functional unit has its inputs set to zero by Step
220
in the next iteration. The entire circuit design is then timed using a conventional timing verifier (also known as a timing analyzer), such as Design Time or Prime Time, both available from Synopsys, Inc., 700 East Middlefield Road, Mountain View, Calif. Step
240
. A chaining table data structure for the current functional unit, which we shall refer to as the current chaining table, is created. Step
245
. Each chaining table data structure should be able to function as a set of tuples. Each tuple contains a functional unit identifier and a functional unit ready time for that functional unit, wherein the ready time has been determined relative to the current functional unit to which the chaining table is attached. In Step
250
the first entry to the current chaining table, such first entry having the ready time of the current functional unit, is added. Next, each functional unit in the transitive fanout of the current functional unit, which shall be referred to as the current fanout unit, is iterated over. Step
260
. The ready time of each current fanout unit is recorded in the current chaining table. Step
270
.
The procedure of
FIG. 2
is limited to entering, in the current chaining table, those functional units which are part of the data flow (i.e. transitive fanout) of the current functional unit. For the purposes of scheduling, it is important to be able to augment the traversal of the RTL network (i.e., RTL description), by Step
260
, to be beyond those functional units reachable solely by a data flow search. In particular, conditional functional units of the RTL network can be related to other functional units of the RTL network by “activation conditions.” A definition of activation condition follows.
An “activation condition” is a signal line or lines of the RTL description which
Du Thuan
Howrey Simon Arnold & White , LLP
Kaplan Jonathan T.
Lee Thomas
Synopsys Inc.
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