Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-23
2003-09-23
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S954000
Reexamination Certificate
active
06624023
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to fabricating flash memory and in particular the present invention relates to using oxygen free radical process cell oxidation to improving the performance of flash memory.
2. Description of the Prior Art
Nonvolatile memory devices include flash EEPROMs (electrical erasable programmable read only memory devices).
FIG. 1
represents the relevant portion of a typical flash memory cell. The memory cell typically includes a substrate
10
and a thin gate dielectric layer
20
(commonly referred to as the tunnel oxide) formed on the surface of the substrate
10
, two stacked gate structure
70
overlying the tunnel oxide
20
. The stacked gate
70
also includes a first polysilicon layer as a floating gate
30
which overlies the tunnel oxide
20
and an interpoly dielectric layer
40
which overlies the floating gate
30
. Lastly, a second polysilicon layer as a control gate
50
overlies the interpoly dielectric layer
40
.
As shown in
FIG. 1
, the stacked gate structure
70
is substantially etched away using conventional etching techniques. However, a problem often occurs at this step involving formation of polystrings
60
. Poly stringers
60
result from incomplete removal of polysilicon layer
30
from the unmasked portions of the wafer during etch. These remaining portions of polysilicon layer
30
material are known as polysilicon layer stringers
60
as shown in
FIG. 1
, which may result in electrically shorting adjacent memory cells. In the other words, the polysilicon layer
30
etching step serves in part to isolate one memory cell from another. However, if a portion of the polysilicon layer
30
is not etched away forms a conductive path (e.g., poly stringer
60
) from one memory cell to another, the memory cells will become electrically shorted.
As shown in
FIG. 2
, the interpoly dielectric layer
40
has a number of important functions including insulating the control gate
50
from the floating gate
30
. Accordingly, it is desirable to form a high quality interpoly dielectric layer
40
. The interpoly dielectric layer
40
is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer
40
having two oxide layers
42
and
46
sandwiching a nitride layer
44
. The thick of bottom oxide layer
42
is about 43 angstrom and top oxide layer
46
is about 62 angstrom. The thick of nitride layer
44
is about 59 angstrom. If the oxide layer
42
,
46
is too thick, the required programming voltage increases undesirably.
As shown in
FIG. 3
, in conventional cell oxidation method, there are dry oxidation, wet oxidation and dry RTO method. They surrounded the surface of the cell to formed thin oxide layer
80
and thick about 100 angstrom. The object of the thin oxide layer
80
provided an insulation protection of the cell. Moreover, the thick of oxide layer is slight, the poly stringer
65
is still exist. The poly stringer
65
which may result in electrically shorting adjacent memory cells. However, if a portion of the poly stringer
65
is not oxidation away formed a conductive path from one memory cell, the memory cells will become electrically shorted. The result is reduced performance of flash memory cell.
As shown in
FIG. 4
, but in those oxidation methods, no matter using dry oxidation, wet oxidation or dry RTO method the problem of serious interpoly dielectric layer
40
encroachment (to formed oxide layer) can't on a valid time programming erased of flash memory. In flash memory, the gate coupling ratio (GCR) value will decrease apparently when the thickness of cell oxidation is increased. This is because of the oxidation encroachment issue between inter poly dielectric layer
40
and polysilicon layer
30
,
50
interface. As shown in
FIG. 4
, the interpoly dielectric layer
40
comprised bottom oxide layer
42
, nitride layer
44
and top oxide layer
46
. When running oxidation process of the cell, serious encroachment issue
42
-
1
,
46
-
1
between bottom oxide layer
42
and first polysilicon layer
30
, top oxide layer
46
and second polysilicon layers
50
. The result is thick of ONO layer (interpoly dielectric layer)
40
increased, the required programming voltage increases undesirably or reduced operating speed.
The method of cell oxidation by dry oxidation process is grown at 875° C. on furnace. The process condition are temperature about 875° C., oxygen gas flow about 10000 sccm and time about 42 minutes 30 seconds. The result diagram as shown
FIG. 4
, the thick of cell oxide layer 80 about 100 angstrom, it is found that a serious encroachment after cell oxidation process is observed. The encroachment oxide is grown between ONO layer
40
and first, second polysilicon layers
30
,
50
interface. This encroachment issue
42
-
1
,
46
-
1
will increase the thickness of ONO layer
40
and decrease gate coupling ratio. Lower gate coupling ratio will degrade channel erase speed.
The method of cell oxidation by wet oxidation process is grown at 820° C. The process condition are the temperature about 820° C., the oxygen gas flow about 4000 sccm, the hydrogen gas flow about 7200 sccm, time about 7 minutes and 10 minutes by annealing with nitrogen gas 15000 sccm. From this method result, diagram same as
FIG. 4
, the thick of cell oxide layer
80
is about 70 angstrom. It is found that cell oxidation by wet oxidation is much more serious ONO encroachment issue
42
-
1
,
46
-
1
than that by dry oxidation. Even if the thickness of wet oxidation only 70 angstrom, the encroachment oxide grown between ONO layer
40
and polysilicon layer
30
,
50
interface is very thick.
The method of cell oxidation by dry RTO process is grown at 1100° C. The process condition are temperature about 1100° C., time about 140 seconds. From this method result, the thick of cell oxide layer
80
is about 120 angstrom. It is found that cell oxidation by RTO also has encroachment issue
42
-
1
,
46
-
1
like dry oxidation, the diagram same as FIG.
4
.
In the prior art of cell oxidation method, no matter using dry oxidation, wet oxidation or dry rapid thermal oxidation (RTO) method the serious ONO encroachment to formed. Then the two oxide layer of ONO layer are thicker, the required programming voltage increases undesirably. The result is reduced performance of flash memory.
SUMMARY OF THE INVENTION
In this invention, they will demonstrate a powerful oxidation method to solving ONO encroachment issue by oxygen free radical process. Scaling down the thickness of encroachment oxide of cell oxidation will improve the gate coupling ratio, however, poly stringer and repaired capability of etching damage are other serious after etched. In order to oxidation poly stringer fully, it is necessary to use thicker cell oxidation process.
In accordance with the present invention, it is a main object of this invention to form cell re-oxidation is described which uses an oxygen free radical process.
It is another object of this invention by using oxygen free radical process cell oxidation improved ONO encroachment between oxide layer and polysilicon layer interface.
It is another object of this invention by using oxygen free radical process cell re-oxidation to eliminate poly stringer.
It is another object of this invention by using oxygen free radical process cell oxidation increased operation efficiency of flash memory.
It is another object of this invention by using oxygen free radical process cell oxidation modified defects after etching process.
It is another object of this invention by utilizing a low thermal budget process for performing a cell re-oxidation, and thus, the short channel effect in a semiconductor structure can be reduced.
In this invention, the method for improving the performance of flash memory. First, a substrate is proved. A tunnel oxide layer is formed on the substrate. There two gate structure are formed on the tunnel oxide layer. The gate structure comprising a first polysilicon layer as a floating gate, an interpoly dielectric layer such as ONO
Han Tzung-Ting
Su Chin-Ta
Su Chun-Lein
Macronix International Co. Ltd.
Nhu David
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