Method for improving the efficiency of weighted random...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S732000, C714S739000

Reexamination Certificate

active

06658616

ABSTRACT:

FIELD OF THE INVENTION
This invention is generally related to VLSI testing and, more particularly, to a method of minimizing test pattern counts by reversing the order of test simulation against a full fault list during weighted random pattern test generation.
DEFINITIONS
The following definitions are being provided to facilitate the understanding of the various terms being used throughout the description of this invention.
Deterministic Test—Electronic chip test data algorithmically derived by determining the necessary chip input stimulus and corresponding expected responses which will detect faults within the chip.
Fault—A representation of a circuit failure which drives an Automatic Test Pattern Generation (ATPG) algorithm to derive a set of circuit inputs which allow for observation of a circuit failure.
WRP—Weighted Random Pattern(s). An electronic chip test methodology which uses specialized hardware to generate test stimuli and collect circuit responses. The stimuli consist of random binary values, one for each circuit input and scan latch, generated by a PRPG and then “weighted” towards a 0 or 1 in order to increase the probability of detecting specific faults. Circuit responses are collected as a signature by a SISR.
PRPG—Pseudo Random Pattern Generator. A hardware device in an electronic chip tester, which, once seeded, produces a repeatable sequence of pseudo-random binary values each time the device is cycled.
SISR—Single Input Signature Register. A response compression device which accumulates one or more circuit responses and compresses them into a signature. Any faulty circuit response absorbed into the signature register circuit inputs will, with a high degree of certainty, cause the resultant signature to be different from what it would be in the absence of a faulty circuit response.
Seed Data—Initial values for the PRPGs and SISRs. A given PRPG seed will always generate the same series of values each time the device is cycled.
Pattern—One test consisting of the application of a clocking sequence along with all other associated activity such as the repeated cycling of the PRPG to refresh the stimuli to be applied to the circuit primary inputs and scan latches and the compression of test results into signature registers.
Test—The order of application of test stimuli I to the electronic chip.
Clocking Sequence—Identifies the circuit clocks and the order in which they are used to release and/or capture values in circuit latches.
Effective Pattern Mask—A string of bits (0 and 1) indicating which patterns of a given weight set the PRPG detect at least one fault when applied to the circuit. There is one bit per pattern. Ineffective patterns can be skipped using special “fast forward” hardware, thus saving test application time.
Weight Set—A set of information which defines the derived biasing for circuit inputs and scan latches. Weights range in value from 0 (never a 1) to 1 (always a 1) and fractional values in between (e.g., a 1 half the time (0.5) or a 1 one quarter of the time (0.25), etc.).
Signature—The resulting set of binary values contained within the SISR which is unique for a correctly responding circuit. A circuit which produces one or more incorrect responses to the applied stimulus would result in a signature which is different, thus identifying a failing circuit.
BACKGROUND OF THE INVENTION
With the increase in chip density, the test data volume associated with deterministically derived tests is becoming prohibitive. Weighted Random Pattern (WRP) testing offers a viable solution to this problem since input stimuli I are dynamically generated , and product responses are compressed into signatures by tester special hardware devices. Thus, the majority of the test data volume associated with WRP consists of a small amount of “weight set” information, stimuli generation and signature compression hardware “seeds” (initialization values), effective pattern masks, and product response signatures.
The WRP testing approach has been used in the industry for many years and much has been published about it as, for instance, in articles by:
J. A. Waicukauski and E. Lindbloom entitled “Fault detection effectiveness of weighted random patterns” published in the Proceedings of the 1988 International Test Conference, pp. 245-255. This paper describes the design of an efficient WRP system wherein performance results are given and deterministic and WRP tests are created for single stuck faults and compared with respect to their ability to detect shorts and transition faults.
J. A. Waicukauski, E. Lindbloom, E. B. Eichelberger and O. P. Forlenza, “A method for generating weighted random test patterns”, published in the IBM Journal of . Research and Development of March 1989, pp. 149-160, wherein the advantage of using weighted random patterns versus deterministic patterns is described., alongside with an algorithm for calculating an initial set of input-weighting factors and a procedure for obtaining complete stuck-fault coverage .
R. Kapur, S. Patil, T. Snethen and T. Williams, “Design of Efficient Weighted Random Pattern Generation System”, International Test Conference, 1994, describes a method for measuring the performance of the system by the number of weight sets and the number of WRP required to achieve a high coverage.
P. Chang, B. Keller and T. Snethen, “A highly efficient weight generation method for handling very large fan-in and XOR-tree designs”, IEEE North Atlantic Test Workshop, 1998, pp. 34-41 described a technique for merging deterministic test patterns to derive weight sets used for WRPT.
In addition to the above publications, the following patents apply:
U.S. Pat. No. 4,801,870 to E. Eichelberger, et al., issued January 1989, describes a method and apparatus for testing Level Sensitive Scan Designs (LSSD) integrated circuits by applying differently configured sequences of pseudo-random patterns; and
U.S. Pat. No. 5,479,414 to P. N. Keller, et al. issued December 1995 describes algorithmically generated test patterns which are structured for efficient test of “scan paths” logic devices, and wherein look ahead test pattern generation and simulation (“fast forward”) schemes achieve a pre-specified fault coverage.
One problem with WRP testing however is that, by its very nature, it depends on pseudo-random patterns to detect faults. Even with biasing (i.e., weighting) to improve the probability of fault detection, WRP patterns tend to require from 2 to 20 times the number of patterns vs. deterministic tests. So, while WRP testing provides test data volume relief, it tends to drive up the cost due to increased test time .
In order to better understand the method described in the present invention an example of the process to obtain a set of WRP test patterns is described hereinafter.
a) Deterministic test patterns are initially derived for a set of selected faults. The number of times a circuit input (either primary input or a scan latch) is required at a “1” value divided by the number of tests requiring a 0 or 1 value determines a unique weight for that input. e.g., a weight of 0.75 would be derived when a 1 is required for 3 out of 4 patterns. By way of example, and with reference to the table shown hereinafter, faults F1, F2, F3, and F4 were selected and the following deterministic patterns were derived for a circuit which has 8 inputs (which could be any mix of primary inputs and/or scan latches):
Input
Input
Input
Input
Input
Input
Input
Input
Fault
1
2
3
4
5
6
7
8
F1
1
1
0
F2
1
0
0
F3
0
0
1
0
1
1
0
F4
0
0
1
0
1
1
Wt
0.33
0.5
0.66
0
0.5
1
1
0
Assuming that the clocking sequences for all the above tests are compatible, the weights for each input are shown in the last row (Wt). Since current PRPG hardware is limited to a fixed set of weights, the above values are rounded accordingly. For example, PRPG using 4 taps would support weights of: 0 (never a 1), 0.0625 ({fraction (1/16)}), 0.125 (⅛), 0.25 (¼), 0.5 (½), 0.75 (¾), 0.875 (⅞), 0.9375 ({fraction (15/16)}), and 1 (never a 0). Thus, the above weights would be adjust

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