Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2001-08-17
2004-07-20
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S780000, C438S781000, C438S789000, C438S790000, C427S489000, C427S503000, C427S579000
Reexamination Certificate
active
06764965
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for improving the coating capability of the low-k dielectric layer, and more particularly to a method for improving coating quality through the pre-wetting process of the baked adhesion promoter layer.
2. Description of the Prior Art
Through advanced semiconductor process in techniques, integrated circuit devices with sub-micron and sub-half-micron features sizes can now be manufactured. This trend toward deep sub-micron technology (i.e., involving feature sizes less than 0.35 microns) has, in turn, driven the need for multilevel interconnect. As a result, circuit performance in the deep sub-micron regime is increasingly a function of the delay time of electronic signals traveling between the millions of gates and transistors presented on the typical integrated circuit chip. Parasitic capacitance and resistance effects resulting from these otherwise passive interconnect structures must therefore be well controlled. Toward this end, recent research emphasizes the use of low resistance metals (e.g., copper) in conjunction with insulating material with low dielectric constant (low-k dielectrics) between metal lines. Low-k dielectric meaning that is a dielectric material, which exhibits a dielectric constant, substantially less than conventional dielectric materials such as silicon dioxide, silicon nitride, and silicon oxynitride. Silicon dioxide, for example, has a dielectric constant of about 4.0. Copper is desirable in that its conductivity is relatively high and it is relatively high resistance of electromigration than many metals (for example, aluminum).
Modern semiconductor processing techniques increasingly employ Chemical-Mechanical Polishing (CMP) in the fabrication of interconnect layers, particularly where the number of layers rises above three and the conductive lines themselves are characterized by a high aspect ratio (e.g., lines on the order of 0.25 &mgr;m width and on the order of 1.0 &mgr;m in height).
In high performance integrated circuits in the sub-0.25 &mgr;m regime, there is a need to fabricate interconnects using so-called damascene techniques. This is because conventional deposition and etching of aluminum-based metallization becomes increasingly difficult at these feature sizes. At the same time, performance considerations call for the use of lower resistivity metals such as copper, which has proven virtually impossible to pattern by using conventional reactive ion etching. Thus, the use of copper for interconnects is of great importance using an attractive damascene techniques and spurred investigation into improving these techniques.
As the dimension of integrated circuit continues to shrink, specific polymeric materials become eminent candidates to be used as inter-layer dielectric (ILD) due to their intrinsic low dielectric constant (k), which is essential for 0.13-micrometer generation and below. They have to be applied through a spin-on coating process and a surfactant material is called adhesion promoter, which is often used to facilitate the coating process and also reinforce the adhesion between the coated low k polymer film and the underlayer, generally, the silicon nitride or silicon carbide.
In this invention, the adhesion promoter layer with thickness about 100 angstroms is coated onto a wafer such as M2 (metal 2) wafer with an etching stop layer and then baked at 150° C. for 120 seconds, wherein the etching stop layer is an inorganic material. The organic polymeric low-k dielectric layer such as SiLK of approximately 3000 angstroms thick is spun-on the wafer, after the wafer is chilled at a 23° C. chill plate for 60 seconds and subsequently baked at 300° C. for 100 seconds. Although the baking step of the adhesion promoter layer can lead to favorable bonding with the underlying etching stop layer, the baked dried surface of the adhesion promoter layer does not facilitate the coating of low-k dielectric material (SiLK).
It is often observed that coating defects appear at the periphery where the coating windows are the most critical if the pre-wetting step is not applied.
According to the above-mentioned description, a method is needed for improving the wettability of adhesion promoter so that a flawless coating of low-k dielectric film can be obtained.
SUMMARY OF THE INVENTION
The object of this invention is to utilize a solvent to improve the wettability for adhesion promoter layer.
The other object of this invention is to provide a method to improve the coating quality through the pre-wetting process of adhesion promoter layer.
The other object of this invention is to provide a method for improving the coating capability of low-k dielectric layer.
According to the objects of above-mentioned, in the preferable embodiment, in order to improve the coating capability of the low-k dielectric layer, the method is provided to use an adhesion promoter layer spun-on coating between the inorganic etching stop layer and low-k dielectric layer, and a pre-wetting process is performed on the adhesion promoter layer to enhance the coating quality when the low-k dielectric layer is spun-on the wafer.
REFERENCES:
patent: 4692398 (1987-09-01), Durham
patent: 4806458 (1989-02-01), Durham
patent: 5962621 (1999-10-01), Beckerdite et al.
patent: 5998103 (1999-12-01), Zhang
patent: 6245690 (2001-06-01), Yau et al.
Hsieh Tsung-Tang
Huang Chih-An
Tsai Cheng-Yuan
Cuneo Kamand
Kilday Lisa
United Microelectronics Corp.
LandOfFree
Method for improving the coating capability of low-k... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for improving the coating capability of low-k..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for improving the coating capability of low-k... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3190183