Method for improving the butted contact resistance of an SRAM by

Details Method for improving the butted contact resistance of an SRAM by Method for improving the butted contact resistance of an SRAM by

1998-07-31

2000-05-02

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438597, 148DIG20, H01L 218244

Patent

active

060571861

ABSTRACT:
Form a butted contact in an SRAM memory device by exposing a contact region on the surface of a doped semiconductor substrate and a conductor stack above a field oxide region on the surface of the substrate. Form an interpolysilicon silicon oxide dielectric layer over the device with an opening framing the contact region and the butt end of the conductor stack near the contact region. Form an undoped upper polysilicon layer on the surface of the SRAM device covering the dielectric layer, the contact region, and the butt end of the conductor stack and then patterned into interconnect and load resistance parts. Form a Vcc mask on the surface of the undoped upper polysilicon layer with a window framing the dielectric layer, the contact region, and the butt end of the conductor stack, leaving an exposed region of the undoped upper polysilicon layer. Ion implant a first dose of Vcc dopant through the window into the undoped upper polysilicon layer at a first energy level, and then ion implant a second dose of Vcc dopant through the window into the buried contact region and the butt end of the conductor stack layer at a higher energy level than the first energy level.

REFERENCES:
patent: 5393687 (1995-02-01), Liang
patent: 5596215 (1997-01-01), Huang
patent: 5607881 (1997-03-01), Huang
patent: 5668051 (1997-09-01), Chen et al.
patent: 5976960 (1999-11-01), Cheffings
patent: 5986328 (1999-11-01), Liaw

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