Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-04-06
2002-05-07
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S643000, C438S660000
Reexamination Certificate
active
06383913
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Filed of the Invention
The present invention generally relates to a method for forming a dielectric material on a semiconductor device, and more particularly to a method for improving the surface wettability of the inorganic dielectric material.
2. Description of the Prior Art
Through advanced semiconductor process in techniques, integrated circuit devices with sub-micron and sub-half-micron features sizes can now be manufactured. This trend toward deep sub-micron technology (i.e., involving feature sizes less than 0.35 microns) has, in turn, driven the need for multilevel interconnect. As a result, circuit performance in the deep sub-micron regime is increasingly a function of the delay time of electronic signals traveling between the millions of gates and transistors presented on the typical integrated circuit chip. Parasitic capacitance and resistance effects resulting from these otherwise passive interconnect structures must therefore be well-controlled. Toward this end, recent researches emphasize the use of low resistance metals (e.g., copper) in conjunction with insulating material with low dielectric constant (low-k dielectrics) between metal lines. Low-k dielectric meaning that is a dielectric material, which exhibits a dielectric constant substantially less than conventional dielectric materials such as silicon dioxide, silicon nitride, and silicon oxynitride. Silicon dioxide, for example, has a dielectric constant of about 4.0. Copper is desirable in that its conductivity is relatively high and it is relatively high resistance of electromigration than many metals (for example, aluminum).
Modern semiconductor processing techniques increasingly employ Chemical-Mechanical Polishing (CMP) in the fabrication of interconnect layers, particularly where the number of layers rises above three and the conductive lines themselves are characterized by a high aspect ratio (e.g., lines on the order of 0.25 &mgr;m in width and on the order of 1.0 &mgr;m in height).
In high performance integrated circuits in the sub-0.25 &mgr;m regime, there is a need to fabricate interconnects using so-called damascene techniques. This is because conventional deposition and etching of aluminum-based metallization becomes increasingly difficult at these feature sizes. At the same time, performance considerations call for the use of lower resistivity metals such as copper, which has proven virtually impossible to pattern by using conventional reactive ion etching. Thus, the use of copper for interconnects is of great importance using an attractive damascene techniques and spurred investigation into improving these techniques.
In addition to use low resistivity metals, such as copper, circuit performance would be straightforward enhanced applying low dielectric constant insulators (k less than 4). In many cases, these low-k materials are spin coated polymers which are incompatible with conventional inorganic silicon-base material deposited by plasma enhanced chemical vapor deposition technique (PECVD), for example, SiN (silicon nitride), SiC (silicon carbide). For forming dual damascene, inorganic dielectric material, such as SiN or SiC, acting as the barrier layer is chemical deposited associated plasma environments. After that, many of low-k material for example, polymer materials spun on SiN or SiC surface. Due to the nature of SiC, however, containing Si—H and Si—CH
3
group, both of the two groups exhibit the hydrophobic characteristics. When organic polymer is coated on the SiC or SiN surface, poor coating/adhesion would occur between the SiC or SiN and the low-k polymer layer. In general, to improve the interface compatibility between organic and inorganic materials, before organic polymer coating an adhesion promoter would be applied and spun on inorganic surface. The improvement of surface compatibility by adhesion promoter could be attributed to both containing the bond of organic, like C—H bond and inorganic bond, like Si—O bond.
According to the above-mentioned description, for improving the adhesion ability between the inorganic dielectric material and the organic polymer, the surface characteristic such as wettability of inorganic dielectric material needs to be enhanced and then surface characteristic needs to be modified, in terms of the transition of hydrophilic to hydrophobic characteristic.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for improving the surface wettability of inorganic dielectric material.
It is another object of this invention to improve the adhesion ability between the inorganic dielectric material and organic polymer.
In the present invention, a method for forming organic low dielectric constant material on a semiconductor device is disclosed. Inorganic dielectric material as barrier layer with hydrophobic characteristic is deposited, followed by a treatment of UV (ultraviolet). Then the surface characteristic of inorganic dielectric material is modified from hydrophobic to less hydrophobic (more hydrophilic) and the surface wettability can be enhanced.
REFERENCES:
patent: 4915772 (1990-04-01), Fehlner et al.
patent: 5380678 (1995-01-01), Yu et al.
patent: 5827755 (1998-10-01), Yonehara et al.
patent: 6118506 (2000-09-01), Yamazaki et al.
Tsai Cheng-Yuan
Yang Ming-Sheng
Lebentritt Michael S.
Powell Goldstein Frazer & Murphy
United Microelectronics Corp.
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